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/linux/include/soc/fsl/qe/
H A Dimmap_qe.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 /* QE I-RAM */
24 __be32 iadd; /* I-RAM Address Register */
25 __be32 idata; /* I-RAM Data Register */
27 __be32 iready; /* I-RAM Ready Register */
63 __be32 cetscr; /* QE time-stamp timer control register */
64 __be32 cetsr1; /* QE time-stamp register 1 */
65 __be32 cetsr2; /* QE time-stamp register 2 */
69 __be16 cercr; /* QE RAM control register */
166 __be16 sirsr1_h; /* SI1 RAM shadow address register high */
[all …]
/linux/drivers/net/wan/
H A Dwanxlfw.S1 /* SPDX-License-Identifier: GPL-2.0-only */
14 0x000 - 0x050 TX#0 0x050 - 0x140 RX#0
15 0x140 - 0x190 TX#1 0x190 - 0x280 RX#1
16 0x280 - 0x2D0 TX#2 0x2D0 - 0x3C0 RX#2
17 0x3C0 - 0x410 TX#3 0x410 - 0x500 RX#3
20 000 5FF 1536 Bytes Dual-Port RAM User Data / BDs
21 600 6FF 256 Bytes Dual-Port RAM User Data / BDs
22 700 7FF 256 Bytes Dual-Port RAM User Data / BDs
23 C00 CBF 192 Bytes Dual-Port RAM Parameter RAM Page 1
24 D00 DBF 192 Bytes Dual-Port RAM Parameter RAM Page 2
[all …]
/linux/include/uapi/linux/
H A Dpmu.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
21 #define PMU_ADB_POLL_OFF 0x21 /* disable ADB auto-poll */
22 #define PMU_WRITE_XPRAM 0x32 /* write eXtended Parameter RAM */
23 #define PMU_WRITE_NVRAM 0x33 /* write non-volatile RAM */
24 #define PMU_READ_XPRAM 0x3a /* read eXtended Parameter RAM */
25 #define PMU_READ_NVRAM 0x3b /* read non-volatile RAM */
26 #define PMU_SET_RTC 0x30 /* set real-time clock */
27 #define PMU_READ_RTC 0x38 /* read real-time clock */
31 #define PMU_PCEJECT 0x4c /* eject PC-card from slot */
35 #define PMU_INT_ACK 0x78 /* read interrupt bits */
[all …]
/linux/drivers/mtd/chips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "RAM/ROM/Flash chip drivers"
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
50 data bits when writing the 'magic' commands to the chips. Saying
53 are expected to be wired to the CPU in 'host-endian' form.
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
[all …]
/linux/include/linux/
H A Dhp_sdc.h2 * HP i8042 System Device Controller -- header
31 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
34 * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
97 #define HP_SDC_STATUS_IRQMASK 0xf0 /* Bits containing "level 1" irq */
104 #define HP_SDC_STATUS_PUP 0x70 /* Successful power-up self test */
134 #define HP_SDC_STR 0x7f /* i8042 self-test result */
139 #define HP_SDC_IM_MASK 0x1f /* these bits not part of cmd/status */
146 #define HP_SDC_CFG_ROLLOVER 0x08 /* WTF is "N-key rollover"? */
149 #define HP_SDC_CFG_KBD_OLD 0x03 /* keyboard code for non-HIL */
167 case 0x1: str = "1820-3712"; break; \
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/linux/Documentation/devicetree/bindings/usb/
H A Dti,omap4-musb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,omap4-musb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@ti.com>
14 Handles SoC-specific integration including PHY interface bridging(ULPI/
23 - ti,omap3-musb
24 - ti,omap4-musb
33 interrupt-names:
36 - const: mc
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H A Dam33xx-usb.txt3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
22 compatible: ti,am335x-usb-phy
25 reg-names: phy
31 - compatible: ti,musb-am33xx
32 - reg: offset and length of "USB Controller Registers", and offset and
[all …]
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,rpm-master-stats.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpm-master-stats.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
16 (particularly around entering hardware-driven low power modes: XO shutdown
17 and total system-wide power collapse) are first made at Master-level, and
20 The Master Stats provide a few useful bits that can be used to assess whether
21 our device has entered the desired low-power mode, how long it took to do so,
26 This scheme has been used on various SoCs in the 2013-2023 era, with some
[all …]
/linux/Documentation/virt/kvm/x86/
H A Dmsr.rst1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
16 ---------------
24 4-byte alignment physical address of a memory area which must be
25 in guest RAM. This memory is expected to hold a copy of the following
42 An odd version indicates an in-progress update.
53 Note that although MSRs are per-CPU entities, the effect of this
63 4-byte aligned physical address of a memory area which must be in
64 guest RAM, plus an enable bit in bit 0. This memory is expected to hold
80 updates of this structure is arbitrary and implementation-dependent.
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgp100.c24 #include "ram.h"
31 gp100_ram_init(struct nvkm_ram *ram) in gp100_ram_init() argument
33 struct nvkm_subdev *subdev = &ram->fb->subdev; in gp100_ram_init()
34 struct nvkm_device *device = subdev->device; in gp100_ram_init()
35 struct nvkm_bios *bios = device->bios; in gp100_ram_init()
47 * (likely selected by 0x9a065c's lower bits?), and the in gp100_ram_init()
53 return -EINVAL; in gp100_ram_init()
92 struct nvkm_ram *ram; in gp100_ram_new() local
94 if (!(ram = *pram = kzalloc_obj(*ram))) in gp100_ram_new()
95 return -ENOMEM; in gp100_ram_new()
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H A Dramgt215.c26 #include "ram.h"
120 hi--; in gt215_link_train_calc()
125 median[i] = ((hi - lo) >> 1) + lo; in gt215_link_train_calc()
138 train->r_100720 = 0; in gt215_link_train_calc()
143 train->r_100720 |= ((median[i] & 0x0f) << (i << 2)); in gt215_link_train_calc()
146 train->r_1111e0 = 0x02000000 | (bin * 0x101); in gt215_link_train_calc()
147 train->r_111400 = 0x0; in gt215_link_train_calc()
154 gt215_link_train(struct gt215_ram *ram) in gt215_link_train() argument
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
157 struct gt215_ramfuc *fuc = &ram->fuc; in gt215_link_train()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
H A Dgf100.c33 struct nvkm_device *device = ltc->subdev.device; in gf100_ltc_cbc_clear()
42 struct nvkm_device *device = ltc->subdev.device; in gf100_ltc_cbc_wait()
44 for (c = 0; c < ltc->ltc_nr; c++) { in gf100_ltc_cbc_wait()
45 for (s = 0; s < ltc->lts_nr; s++) { in gf100_ltc_cbc_wait()
58 struct nvkm_device *device = ltc->subdev.device; in gf100_ltc_zbc_clear_color()
69 struct nvkm_device *device = ltc->subdev.device; in gf100_ltc_zbc_clear_depth()
95 struct nvkm_subdev *subdev = &ltc->subdev; in gf100_ltc_lts_intr()
96 struct nvkm_device *device = subdev->device; in gf100_ltc_lts_intr()
113 struct nvkm_device *device = ltc->subdev.device; in gf100_ltc_intr()
119 for (s = 0; s < ltc->lts_nr; s++) in gf100_ltc_intr()
[all …]
/linux/arch/m68k/include/asm/
H A Dmac_iop.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 /* IOP status/control register bits: */
24 #define IOP_BYPASS 0x01 /* bypass-mode hardware access */
38 /* IOP reference numbers, used by the globally-visible iop_xxx functions */
78 __u8 ram_addr_hi; /* shared RAM address hi byte */
80 __u8 ram_addr_lo; /* shared RAM address lo byte */
84 __u8 ram_data; /* RAM data byte at ramhi/lo */
88 /* Bypass-mode hardware access registers */
106 __u8 wcrc; /* write 2-byte crc to disk */
114 __u8 wzeroes; /* mode reg: 1's clr bits, 0's are x */
[all …]
/linux/arch/powerpc/platforms/512x/
H A Dmpc512x_lpbfifo.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2013-2015 Alexander Popov <alex.popov@linux.com>.
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
49 * A data transfer from RAM to some device on LPB is finished
53 * But for a data transfer from some device on LPB to RAM we don't enable
61 * mpc512x_lpbfifo_irq - IRQ handler for LPB FIFO
76 if (!req || req->dir == MPC512X_LPBFIFO_REQ_DIR_READ) { in mpc512x_lpbfifo_irq()
81 status = in_be32(&lpbfifo.regs->status); in mpc512x_lpbfifo_irq()
83 dev_err(dev, "DMA transfer from RAM to peripheral failed\n"); in mpc512x_lpbfifo_irq()
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-class-rc6 The rc/ class sub-directory belongs to the Remote Controller
33 Writing "-proto" will remove a protocol from the list of enabled
51 expected value of the bits set in the filter mask.
63 Sets the scancode filter mask of bits to compare.
64 Use in combination with /sys/class/rc/rcN/filter to set the bits
83 "rc-5 nec nec-x rc-6-0 rc-6-6a-24 [rc-6-6a-32] rc-6-mce"
86 "rc-5", "rc-6" have their different bit length encodings
109 set the expected value of the bits set in the wakeup filter mask
114 suspend to RAM or power off.
125 Sets the scancode wakeup filter mask of bits to compare.
[all …]
H A Dsysfs-driver-w1_therm7 (typical -55 degC to 125 degC), if not values will be trimmed
11 master level, refer to Documentation/w1/w1-generic.rst for
26 * 'save': save device RAM to EEPROM
27 * 'restore': restore EEPROM data in device RAM
41 * '-xx': xx is kernel error when reading power status
53 will be changed only in device RAM, so it will be cleared when
55 values after power-on. Read or write are :
59 * '-xx': xx is kernel error when reading the resolution
62 Some DS18B20 clones are fixed in 12-bit resolution, so the
83 device support this feature). It takes 94ms in 9bits
[all …]
/linux/fs/pstore/
H A Dram_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * Choose whether access to the RAM zone requires locking or not. If a zone
17 * If a PRZ should only have a single-boot lifetime, this marks it as
23 * struct persistent_ram_zone - Details of a persistent RAM zone (PRZ)
26 * @paddr: physical address of the mapped RAM area
30 * @flags: holds PRZ_FLAGS_* bits
35 * pointer to actual RAM area managed by this PRZ
37 * bytes in @buffer->data (not including any trailing ECC bytes)
40 * pointer into @buffer->data containing ECC bytes for @buffer->data
42 * pointer into @buffer->data containing ECC bytes for @buffer header
[all …]
/linux/arch/sparc/include/uapi/asm/
H A Dasi.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
37 /* SPARCstation-5: only 6 bits are decoded. */
69 /* Block-copy operations are available only on certain V8 cpus. */
79 /* Block-fill operations are available on certain V8 cpus */
83 * the available ASI's for physical ram pass-through, but I don't have
89 #define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
90 #define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
91 #define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
92 #define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
137 #define ASI_PL 0x88 /* Primary, implicit, l-endian */
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/linux/Documentation/arch/arm/
H A Dtcm.rst2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
32 place you put it, it will mask any underlying RAM from the
33 CPU so it is usually wise not to overlap any physical RAM with
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam3517.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
11 /delete-node/ &aes1_target;
12 /delete-node/ &aes2_target;
24 operating-points-v2 = <&cpu0_opp_table>;
26 clock-latency = <300000>; /* From legacy driver */
30 cpu0_opp_table: opp-table {
31 compatible = "operating-points-v2-ti-cpu";
38 opp-50-300000000 {
40 opp-hz = /bits/ 64 <300000000>;
[all …]
/linux/arch/powerpc/mm/nohash/
H A Dkaslr_booke.c1 // SPDX-License-Identifier: GPL-2.0-only
52 /* Rotate by odd number of bits and XOR. */ in rotate_xor()
53 hash = (hash << ((sizeof(hash) * 8) - 7)) | (hash >> 7); in rotate_xor()
68 /* build-specific string for starting entropy. */ in get_boot_seed()
85 prop = fdt_getprop_w(fdt, node, "kaslr-seed", &len); in get_kaslr_seed()
116 /* check for overlap with static reservations in /reserved-memory */ in overlaps_reserved_region()
132 len -= 4 * regions.reserved_mem_addr_cells; in overlaps_reserved_region()
139 len -= 4 * regions.reserved_mem_size_cells; in overlaps_reserved_region()
204 prop = fdt_getprop(fdt, node, "linux,initrd-start", &len); in get_initrd_range()
209 prop = fdt_getprop(fdt, node, "linux,initrd-end", &len); in get_initrd_range()
[all …]
/linux/drivers/net/ethernet/amd/
H A D7990.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * 7990.h -- LANCE ethernet IC generic routines.
4 * This is an attempt to separate out the bits of various ethernet
11 * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
32 * too long (and overflow the RAM on shared-memory cards like the HP LANCE.
41 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
42 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
52 volatile unsigned char rmd1_bits; /* descriptor bits */
62 volatile unsigned char tmd1_bits; /* descriptor bits */
74 volatile unsigned short mode; /* Pre-set mode (reg. 15) */
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_type.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
32 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
33 (R)->next_to_clean - (R)->next_to_use - 1)
208 * Mode2: Filter for non-tunneled traffic
288 u16 sr_size; /* Shadow RAM size in words */
545 /* for multi-function MACs */
685 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
689 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
691 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
[all …]
/linux/arch/m68k/coldfire/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * head.S -- common startup code for ColdFire CPUs.
7 * (C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>.
14 #include <asm/asm-offsets.h>
26 * that do not have their RAM starting at address 0, and it only
40 * but the DCMR register is virtually identical - give or take
41 * a couple of bits. The only exception is the 5272 devices, their
66 negl %d0 /* negate bits */
119 * During startup we store away the RAM setup. These are not in the
182 movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
166 IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
225 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
226 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
[all …]

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