xref: /linux/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml (revision 9f32a03e3e0d372c520d829dd4da6022fe88832a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
8
9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
12description:
13  On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
14  generation and control of clock signals for the IP modules, generation and
15  control of resets, and control over booting, low power consumption and power
16  supply domains.
17
18properties:
19  compatible:
20    enum:
21      - renesas,r9a09g047-cpg # RZ/G3E
22      - renesas,r9a09g056-cpg # RZ/V2N
23      - renesas,r9a09g057-cpg # RZ/V2H
24
25  reg:
26    maxItems: 1
27
28  clocks:
29    items:
30      - description: AUDIO_EXTAL clock input
31      - description: RTXIN clock input
32      - description: QEXTAL clock input
33
34  clock-names:
35    items:
36      - const: audio_extal
37      - const: rtxin
38      - const: qextal
39
40  '#clock-cells':
41    description: |
42      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
43        and a core clock reference, as defined in
44        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
45      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
46        a module number.  The module number is calculated as the CLKON register
47        offset index multiplied by 16, plus the actual bit in the register
48        used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
49        calculation is (1 * 16 + 3) = 0x13.
50    const: 2
51
52  '#power-domain-cells':
53    const: 0
54
55  '#reset-cells':
56    description:
57      The single reset specifier cell must be the reset number. The reset number
58      is calculated as the reset register offset index multiplied by 16, plus the
59      actual bit in the register used to reset the specific IP block. For example,
60      for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
61    const: 1
62
63required:
64  - compatible
65  - reg
66  - clocks
67  - clock-names
68  - '#clock-cells'
69  - '#power-domain-cells'
70  - '#reset-cells'
71
72additionalProperties: false
73
74examples:
75  - |
76    clock-controller@10420000 {
77        compatible = "renesas,r9a09g057-cpg";
78        reg = <0x10420000 0x10000>;
79        clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
80        clock-names = "audio_extal", "rtxin", "qextal";
81        #clock-cells = <2>;
82        #power-domain-cells = <0>;
83        #reset-cells = <1>;
84    };
85