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/linux/arch/x86/purgatory/
H A Dentry64.S62 rax: .quad 0x0
63 rcx: .quad 0x0
64 rdx: .quad 0x0
65 rbx: .quad 0x0
66 rsp: .quad 0x0
67 rbp: .quad 0x0
68 rsi: .quad 0x0
69 rdi: .quad 0x0
70 r8: .quad 0x0
71 r9: .quad 0x0
[all …]
/linux/arch/s390/kernel/
H A Dvmlinux.lds.S254 QUAD(startup_continue) /* entry */
255 QUAD(__bss_start - _stext) /* image_size */
256 QUAD(__bss_stop - __bss_start) /* bss_size */
257 QUAD(__boot_data_start) /* bootdata_off */
258 QUAD(__boot_data_end - __boot_data_start) /* bootdata_size */
259 QUAD(__boot_data_preserved_start) /* bootdata_preserved_off */
260 QUAD(__boot_data_preserved_end -
262 QUAD(__got_start) /* got_start */
263 QUAD(__got_end) /* got_end */
264 QUAD(_eamode31 - _samode31) /* amode31_size */
[all …]
/linux/lib/crypto/x86/
H A Dsha512-ssse3-asm.S380 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
381 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
382 .quad 0x3956c25bf348b538,0x59f111f1b605d019
383 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
384 .quad 0xd807aa98a3030242,0x12835b0145706fbe
385 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
386 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
387 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
388 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
389 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
[all …]
H A Dsha512-avx-asm.S381 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
382 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
383 .quad 0x3956c25bf348b538,0x59f111f1b605d019
384 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
385 .quad 0xd807aa98a3030242,0x12835b0145706fbe
386 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
387 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
388 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
389 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
390 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
[all …]
H A Dsha512-avx2-asm.S696 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
697 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
698 .quad 0x3956c25bf348b538,0x59f111f1b605d019
699 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
700 .quad 0xd807aa98a3030242,0x12835b0145706fbe
701 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
702 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
703 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
704 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
705 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
[all …]
/linux/arch/riscv/kernel/
H A Defi-header.S50 .quad 0 // ImageBase
68 .quad 0 // SizeOfStackReserve
69 .quad 0 // SizeOfStackCommit
70 .quad 0 // SizeOfHeapReserve
71 .quad 0 // SizeOfHeapCommit
75 .quad 0 // ExportTable
76 .quad 0 // ImportTable
77 .quad 0 // ResourceTable
78 .quad 0 // ExceptionTable
79 .quad 0 // CertificationTable
[all …]
/linux/arch/loongarch/kernel/
H A Defi-header.S37 .quad 0 /* ImageBase */
55 .quad 0 /* SizeOfStackReserve */
56 .quad 0 /* SizeOfStackCommit */
57 .quad 0 /* SizeOfHeapReserve */
58 .quad 0 /* SizeOfHeapCommit */
62 .quad 0 /* ExportTable */
63 .quad 0 /* ImportTable */
64 .quad 0 /* ResourceTable */
65 .quad 0 /* ExceptionTable */
66 .quad 0 /* CertificationTable */
[all …]
/linux/lib/crc/arm/
H A Dcrc32-core.S67 .quad 0x0000000154442bd4
68 .quad 0x00000001c6e41596
77 .quad 0x00000001751997d0
78 .quad 0x00000000ccaa009e
84 .quad 0x0000000163cd6124
85 .quad 0x00000000FFFFFFFF
94 .quad 0x00000001DB710641
95 .quad 0x00000001F7011641
98 .quad 0x00000000740eef02
99 .quad 0x000000009e4addf8
[all …]
H A Dcrc-t10dif-core.S440 .quad 0x0000000000006123 // x^(8*128) mod G(x)
441 .quad 0x0000000000002295 // x^(8*128+64) mod G(x)
443 .quad 0x0000000000001069 // x^(4*128) mod G(x)
444 .quad 0x000000000000dd31 // x^(4*128+64) mod G(x)
446 .quad 0x000000000000857d // x^(2*128) mod G(x)
447 .quad 0x0000000000007acc // x^(2*128+64) mod G(x)
449 .quad 0x000000000000a010 // x^(1*128) mod G(x)
450 .quad 0x0000000000001faa // x^(1*128+64) mod G(x)
452 .quad 0x1368000000000000 // x^48 * (x^48 mod G(x))
453 .quad 0x2d56000000000000 // x^48 * (x^80 mod G(x))
[all …]
/linux/arch/arm64/kernel/
H A Defi-header.S52 .quad 0 // ImageBase
70 .quad 0 // SizeOfStackReserve
71 .quad 0 // SizeOfStackCommit
72 .quad 0 // SizeOfHeapReserve
73 .quad 0 // SizeOfHeapCommit
77 .quad 0 // ExportTable
78 .quad 0 // ImportTable
79 .quad 0 // ResourceTable
80 .quad 0 // ExceptionTable
81 .quad 0 // CertificationTable
[all …]
/linux/lib/crypto/arm64/
H A Dsha2-armv8.pl294 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
295 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
296 .quad 0x3956c25bf348b538,0x59f111f1b605d019
297 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
298 .quad 0xd807aa98a3030242,0x12835b0145706fbe
299 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
300 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
301 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
302 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
303 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
[all …]
/linux/drivers/firmware/efi/libstub/
H A Dzboot-header.S50 .quad 0
68 .quad 0, 0, 0, 0
75 .quad 0 // ExportTable
76 .quad 0 // ImportTable
77 .quad 0 // ResourceTable
78 .quad 0 // ExceptionTable
79 .quad 0 // CertificationTable
80 .quad 0 // BaseRelocationTable
/linux/drivers/scsi/megaraid/
H A Dmegaraid_sas_fp.c377 struct MR_QUAD_ELEMENT *quad; in MR_GetSpanBlock() local
384 quad = &pSpanBlock->block_span_info.quad[j]; in MR_GetSpanBlock()
386 if (le32_to_cpu(quad->diff) == 0) in MR_GetSpanBlock()
388 if (le64_to_cpu(quad->logStart) <= row && row <= in MR_GetSpanBlock()
389 le64_to_cpu(quad->logEnd) && (mega_mod64(row - le64_to_cpu(quad->logStart), in MR_GetSpanBlock()
390 le32_to_cpu(quad->diff))) == 0) { in MR_GetSpanBlock()
393 blk = mega_div64_32((row-le64_to_cpu(quad->logStart)), le32_to_cpu(quad->diff)); in MR_GetSpanBlock()
395 blk = (blk + le64_to_cpu(quad->offsetInSpan)) << raid->stripeShift; in MR_GetSpanBlock()
429 struct MR_QUAD_ELEMENT *quad; in mr_spanset_get_span_block() local
445 quad = &map->raidMap.ldSpanMap[ld]. in mr_spanset_get_span_block()
[all …]
/linux/arch/arm/boot/compressed/
H A Defi-header.S97 .quad 0 @ ExportTable
98 .quad 0 @ ImportTable
99 .quad 0 @ ResourceTable
100 .quad 0 @ ExceptionTable
101 .quad 0 @ CertificationTable
102 .quad 0 @ BaseRelocationTable
/linux/arch/x86/boot/
H A Dheader.S97 .quad 0 # ImageBase
121 .quad 0 # SizeOfStackReserve
122 .quad 0 # SizeOfStackCommit
123 .quad 0 # SizeOfHeapReserve
124 .quad 0 # SizeOfHeapCommit
129 .quad 0 # ExportTable
130 .quad 0 # ImportTable
131 .quad 0 # ResourceTable
132 .quad 0 # ExceptionTable
133 .quad 0 # CertificationTable
[all …]
/linux/Documentation/devicetree/bindings/mips/loongson/
H A Ddevices.yaml20 - description: Classic Loongson64 Quad Core + LS7A
24 - description: Classic Loongson64 Quad Core + RS780E
32 - description: Generic Loongson64 Quad Core + LS7A
36 - description: Virtual Loongson64 Quad Core + VirtIO
/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv1013.yaml78 vcc-quad-supply:
95 adi,quad-se-mode:
121 - vcc-quad-supply
149 vcc-quad-supply = <&vcc_quad>;
150 adi,quad-se-mode = "diff";
H A Dadi,admv1014.yaml66 vcc-quad-supply:
92 adi,quad-se-mode:
112 - vcc-quad-supply
138 vcc-quad-supply = <&vcc_quad>;
140 adi,quad-se-mode = "diff";
/linux/arch/x86/kernel/
H A Drelocate_kernel_64.S33 SYM_DATA_LOCAL(saved_rsp, .quad 0)
34 SYM_DATA_LOCAL(saved_cr0, .quad 0)
35 SYM_DATA_LOCAL(saved_cr3, .quad 0)
36 SYM_DATA_LOCAL(saved_cr4, .quad 0)
38 SYM_DATA(kexec_va_control_page, .quad 0)
39 SYM_DATA(kexec_pa_table_page, .quad 0)
40 SYM_DATA(kexec_pa_swap_page, .quad 0)
41 SYM_DATA_LOCAL(pa_backup_pages_map, .quad 0)
42 SYM_DATA(kexec_debug_8250_mmio32, .quad 0)
50 .quad 0x00cf9a000000ffff /* __KERNEL32_CS */
[all …]
/linux/drivers/counter/
H A DKconfig31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
38 encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).
41 operation on the respective count value attribute. The 104-QUAD-8
/linux/arch/alpha/lib/
H A Dev6-memset.S87 mskql $4,$16,$4 # U : clear relevant parts of the quad
99 * We are now guaranteed to be quad aligned, with at least
100 * one partial quad to write.
126 * through unrolled loop. Do a quad at a time to get us 0mod64
209 mskqh $7,$6,$2 # U : Mask final quad
265 mskql $4,$16,$4 # U : clear relevant parts of the quad
277 * We are now guaranteed to be quad aligned, with at least
278 * one partial quad to write.
304 * through unrolled loop. Do a quad at a time to get us 0mod64
387 mskqh $7,$6,$2 # U : Mask final quad
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c722 * ice_write_quad_ptp_reg_eth56g - Write a PHY quad register
747 * ice_read_quad_ptp_reg_eth56g - Read a PHY quad register
1095 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block
1097 * @port: the quad to read from
2695 * ice_fill_quad_msg_e82x - Fill message data for quad register access
2698 * @quad: the quad to access
2701 * Fill a message buffer for accessing a register in a quad shared between
2706 * * %-EINVAL - invalid quad number
2709 struct ice_sbq_msg_input *msg, u8 quad, in ice_fill_quad_msg_e82x() argument
2714 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) in ice_fill_quad_msg_e82x()
[all …]
H A Dice_ptp.h43 * |--- quad offset is always 0
44 * ---- quad number
48 * | register block for quad 0 | register block for quad 1 |
54 * | --- quad offset*
55 * ---- quad number
57 * * PHY port 5 is port 1 in quad 1
103 * @block: which memory block (quad or port) the timestamps are captured in
128 /* Quad and port information for initializing timestamp blocks */
/linux/tools/testing/selftests/sgx/
H A Dtest_encl_bootstrap.S15 .quad encl_ssa_tcs1 # OSSA
18 .quad encl_entry # OENTRY
29 .quad encl_ssa_tcs2 # OSSA
32 .quad encl_entry # OENTRY
/linux/include/linux/mtd/
H A Dspi-nor.h32 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
33 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
37 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
38 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
58 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
59 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
63 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
64 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
121 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
219 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
[all …]

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