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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 vcm-supply:
42 vcc-drv-supply:
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H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
38 vcm-supply:
40 Common-mode voltage regulator.
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/linux/drivers/counter/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
38 encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).
41 operation on the respective count value attribute. The 104-QUAD-8
58 module will be called ftm-quaddec.
69 will be called intel-qep.
79 module will be called interrupt-cnt.
91 module will be called microchip-tcb-capture.
98 SoCs. This IP supports both 16-bit and 32-bit phase counting mode
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H A Dftm-quaddec.c1 // SPDX-License-Identifier: GPL-2.0
37 if (ftm->big_endian) in ftm_read()
38 *data = ioread32be(ftm->ftm_base + offset); in ftm_read()
40 *data = ioread32(ftm->ftm_base + offset); in ftm_read()
45 if (ftm->big_endian) in ftm_write()
46 iowrite32be(data, ftm->ftm_base + offset); in ftm_write()
48 iowrite32(data, ftm->ftm_base + offset); in ftm_write()
90 /* Select quad mode, reset other fields to zero */ in ftm_quaddec_init()
135 mutex_lock(&ftm->ftm_quaddec_mutex); in ftm_quaddec_set_prescaler()
144 mutex_unlock(&ftm->ftm_quaddec_mutex); in ftm_quaddec_set_prescaler()
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/linux/Documentation/devicetree/bindings/regulator/
H A Ddlg,da9121.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adam Ward <Adam.Ward.opensource@diasemi.com>
13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
20 { TIME_SYNC, { 4, -1 }, { 0, 0 }},
21 { ONE_PPS, { -1, 5 }, { 0, 11 }},
30 { TIME_SYNC, { 4, -1 }, { 11, 0 }},
31 { ONE_PPS, { -1, 5 }, { 0, 9 }},
40 { ONE_PPS, { -1, 5 }, { 0, 1 }},
53 { GNSS, { 1, -1 }, { 0, 0 }},
55 { UFL1, { -1, 0 }, { 0, 1 }},
57 { UFL2, { 3, -1 }, { 0, 0 }},
62 return !pf->adapter ? NULL : pf->adapter->ctrl_pf; in ice_get_ctrl_pf()
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H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
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H A Dice_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
90 * ice_dump_phy_type - helper function to dump phy_type
117 * ice_set_mac_type - Sets MAC type
125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) in ice_set_mac_type()
126 return -ENODEV; in ice_set_mac_type()
128 switch (hw->device_id) { in ice_set_mac_type()
135 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
156 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
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/linux/drivers/mtd/spi-nor/
H A Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
56 * Quad Enable Requirements (QER):
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
59 * instruction phase.
60 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
63 * Writing only one byte to the status register has the side-effect of
67 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70 * - 011b: QE is bit 7 of status register 2. It is set via Write status
74 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
31 * For everything but full-chip erase; probably could be much smaller, but kept
37 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
48 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
61 switch (nor->cmd_ext_type) { in spi_nor_get_cmd_ext()
63 return ~op->cmd.opcode; in spi_nor_get_cmd_ext()
66 return op->cmd.opcode; in spi_nor_get_cmd_ext()
69 dev_err(nor->dev, "Unknown command extension type\n"); in spi_nor_get_cmd_ext()
75 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
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/linux/drivers/spi/
H A Dspi-falcon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #define DRV_NAME "sflash-falcon"
43 /* Dummy Phase Length */
52 /* SCK Rise-edge Position */
58 /* SCK Fall-edge Position */
82 /* 8-bit multiplexed */
100 struct device *dev = &spi->dev; in falcon_sflash_xfer()
101 struct falcon_sflash *priv = spi_controller_get_devdata(spi->controller); in falcon_sflash_xfer()
102 const u8 *txp = t->tx_buf; in falcon_sflash_xfer()
103 u8 *rxp = t->rx_buf; in falcon_sflash_xfer()
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/linux/drivers/usb/gadget/udc/cdns2/
H A Dcdns2-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
14 #include <linux/dma-direction.h>
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
45 /* EP0CS - bitmasks. */
54 /* Send STALL in the data stage phase. */
59 /* EP0FIFO - bitmasks. */
70 * struct cdns2_epx_base - base endpoint registers.
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
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/linux/sound/usb/
H A Dquirks-table.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
72 #define QUIRK_COMPOSITE_END { .ifnum = -1 }
127 /* Creative BT-D1 */
146 /* E-Mu 0202 USB */
148 /* E-Mu 0404 USB */
150 /* E-Mu Tracker Pre */
152 /* E-Mu 0204 USB */
214 * Logitech QuickCam: bDeviceClass is vendor-specific, so generic interface
256 YAMAHA_DEVICE(0x100c, "UC-MX"),
257 YAMAHA_DEVICE(0x100d, "UC-KX"),
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/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
200 "BriefDescription": "Read-write data cache collisions"
210 …phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtrac…
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
395 …-word boundary, which causes it to require an additional slice than than what normally would be re…
430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
450 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
455 "BriefDescription": "D-side L2 MRU touch commands sent to the L2"
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/linux/drivers/pci/
H A Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
106 int ret = -ENOTTY; in pcie_failed_link_retrain()
109 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
117 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
175 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
176 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
177 (f->vendor == dev->vendor || in pci_do_fixups()
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