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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 vcm-supply:
42 vcc-drv-supply:
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H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
38 vcm-supply:
40 Common-mode voltage regulator.
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/linux/drivers/counter/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
38 encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).
41 operation on the respective count value attribute. The 104-QUAD-8
58 module will be called ftm-quaddec.
69 will be called intel-qep.
79 module will be called interrupt-cnt.
91 module will be called microchip-tcb-capture.
98 SoCs. This IP supports both 16-bit and 32-bit phase counting mode
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H A Dftm-quaddec.c1 // SPDX-License-Identifier: GPL-2.0
37 if (ftm->big_endian) in ftm_read()
38 *data = ioread32be(ftm->ftm_base + offset); in ftm_read()
40 *data = ioread32(ftm->ftm_base + offset); in ftm_read()
45 if (ftm->big_endian) in ftm_write()
46 iowrite32be(data, ftm->ftm_base + offset); in ftm_write()
48 iowrite32(data, ftm->ftm_base + offset); in ftm_write()
90 /* Select quad mode, reset other fields to zero */ in ftm_quaddec_init()
135 mutex_lock(&ftm->ftm_quaddec_mutex); in ftm_quaddec_set_prescaler()
144 mutex_unlock(&ftm->ftm_quaddec_mutex); in ftm_quaddec_set_prescaler()
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/linux/Documentation/devicetree/bindings/regulator/
H A Ddlg,da9121.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adam Ward <Adam.Ward.opensource@diasemi.com>
13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
19 { TIME_SYNC, { 4, -1 }, { 0, 0 }},
20 { ONE_PPS, { -1, 5 }, { 0, 11 }},
29 { TIME_SYNC, { 4, -1 }, { 11, 0 }},
30 { ONE_PPS, { -1, 5 }, { 0, 9 }},
39 { ONE_PPS, { -1, 5 }, { 0, 1 }},
51 { SDP0, { -1, 0 }, { 0, 1 }},
52 { SDP1, { 1, -1 }, { 0, 0 }},
53 { SDP2, { -1, 2 }, { 0, 1 }},
54 { SDP3, { 3, -1 }, { 0, 0 }},
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H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
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H A Dice_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
90 * ice_dump_phy_type - helper function to dump phy_type
117 * ice_set_mac_type - Sets MAC type
125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) in ice_set_mac_type()
126 return -ENODEV; in ice_set_mac_type()
128 switch (hw->device_id) { in ice_set_mac_type()
135 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
156 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
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/linux/drivers/mtd/spi-nor/
H A Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
56 * Quad Enable Requirements (QER):
57 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
59 * instruction phase.
60 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
63 * Writing only one byte to the status register has the side-effect of
67 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
70 * - 011b: QE is bit 7 of status register 2. It is set via Write status
74 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
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/linux/drivers/spi/
H A Dspi-falcon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #define DRV_NAME "sflash-falcon"
43 /* Dummy Phase Length */
52 /* SCK Rise-edge Position */
58 /* SCK Fall-edge Position */
82 /* 8-bit multiplexed */
101 struct device *dev = &spi->dev; in falcon_sflash_xfer()
102 struct falcon_sflash *priv = spi_controller_get_devdata(spi->controller); in falcon_sflash_xfer()
103 const u8 *txp = t->tx_buf; in falcon_sflash_xfer()
104 u8 *rxp = t->rx_buf; in falcon_sflash_xfer()
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H A Dspi-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * 2002-2007 (c) MontaVista Software, Inc.
56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
120 if (!xspi->tx_ptr) { in xilinx_spi_tx()
121 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
125 switch (xspi->bytes_per_word) { in xilinx_spi_tx()
127 data = *(u8 *)(xspi->tx_ptr); in xilinx_spi_tx()
130 data = *(u16 *)(xspi->tx_ptr); in xilinx_spi_tx()
133 data = *(u32 *)(xspi->tx_ptr); in xilinx_spi_tx()
137 xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); in xilinx_spi_tx()
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H A Dspi-rspi.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on spi-sh.c:
21 #include <linux/dma-mapping.h>
40 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
68 /* SPCR - Control Register */
77 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
78 /* QSPI on R-Car Gen2 only */
79 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
80 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
82 /* SSLP - Slave Select Polarity Register */
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H A Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
160 * struct qspi_platform_data - zynqmp qspi platform data structure
168 * struct zynqmp_qspi - Defines qspi driver instance
214 * zynqmp_gqspi_read - For GQSPI controller read operation
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/linux/drivers/usb/gadget/udc/cdns2/
H A Dcdns2-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
14 #include <linux/dma-direction.h>
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
45 /* EP0CS - bitmasks. */
54 /* Send STALL in the data stage phase. */
59 /* EP0FIFO - bitmasks. */
70 * struct cdns2_epx_base - base endpoint registers.
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
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/linux/sound/usb/
H A Dquirks-table.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
72 #define QUIRK_COMPOSITE_END { .ifnum = -1 }
127 /* Creative BT-D1 */
146 /* E-Mu 0202 USB */
148 /* E-Mu 0404 USB */
150 /* E-Mu Tracker Pre */
152 /* E-Mu 0204 USB */
214 * Logitech QuickCam: bDeviceClass is vendor-specific, so generic interface
256 YAMAHA_DEVICE(0x100c, "UC-MX"),
257 YAMAHA_DEVICE(0x100d, "UC-KX"),
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/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
200 "BriefDescription": "Read-write data cache collisions"
210 …phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtrac…
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
395 …-word boundary, which causes it to require an additional slice than than what normally would be re…
430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
450 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
455 "BriefDescription": "D-side L2 MRU touch commands sent to the L2"
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/linux/drivers/pci/controller/dwc/
H A Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
37 #include "pcie-designware.h"
82 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
118 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
183 /* PCIe Port Logic registers (memory-mapped) */
196 /* PHY registers (not memory-mapped) */
233 WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && in imx_pcie_grp_offset()
234 imx_pcie->drvdata->variant != IMX8MQ_EP && in imx_pcie_grp_offset()
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/linux/arch/mips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
144 bool "Generic board-agnostic MIPS kernel"
286 Build a generic DT-based kernel image that boots on select
287 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
379 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
380 DECstation porting pages on <http://decstation.unix-ag.org/>.
444 Olivetti M700-10 workstations.
481 bool "Loongson 32-bit family of machines"
501 This enables support for the Loongson-1 family of machines.
503 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
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/linux/lib/zstd/decompress/
H A Dhuf_decompress.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
8 * - FSE+HUF source repository : https://github.com/Cyan4973/FiniteStateEntropy
10 * This source code is licensed under both the BSD-style license (found in the
13 * You may select, at your option, one of the above-listed licenses.
81 #define HUF_ALIGN(x, a) HUF_ALIGN_MASK((x), (a) - 1)
135 /*-***************************/
137 /*-***************************/
149 size_t const bitsConsumed = lastByte ? 8 - ZSTD_highbit32(lastByte) : 0; in HUF_initFastDStream()
160 * ip [in/out] - The input pointers, must be updated to reflect what is consumed.
161 * op [in/out] - The output pointers, must be updated to reflect what is written.
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/linux/drivers/pci/
H A Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
41 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) in pcie_lbms_seen()
102 int ret = -ENOTTY; in pcie_failed_link_retrain()
105 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
112 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
173 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
174 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
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