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/linux/Documentation/devicetree/bindings/mips/loongson/
H A Ddevices.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
20 - description: Classic Loongson64 Quad Core + LS7A
22 - const: loongson,loongson64c-4core-ls7a
24 - description: Classic Loongson64 Quad Core + RS780E
26 - const: loongson,loongson64c-4core-rs780e
28 - description: Classic Loongson64 Octa Core + RS780E
30 - const: loongson,loongson64c-8core-rs780e
[all …]
/linux/lib/crypto/arm64/
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
17 * assemblers both consider the SHA-512 instructions to be part of the
20 * versions.) "sha3" doesn't make a lot of sense, since SHA-512 is part
21 * of the SHA-2 family of algorithms, and also the Arm Architecture
25 .arch armv8-a+sha3
28 * The SHA-512 round constants
33 .quad 0x428a2f98d728ae22, 0x7137449123ef65cd
34 .quad 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
35 .quad 0x3956c25bf348b538, 0x59f111f1b605d019
[all …]
/linux/Documentation/devicetree/bindings/arm/
H A Dactions.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
19 - items:
20 - enum:
21 - allo,sparky # Allo.com Sparky
22 - cubietech,cubieboard6 # Cubietech CubieBoard6
[all …]
/linux/Documentation/arch/arm/
H A Dmarvell.rst13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
[all …]
/linux/Documentation/devicetree/bindings/arm/marvell/
H A Darmada-7k-8k.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR X11)
3 ---
4 $id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gregory CLEMENT <gregory.clement@bootlin.com>
18 - description: Armada 7020 SoC
20 - const: marvell,armada7020
21 - const: marvell,armada-ap806-dual
22 - const: marvell,armada-ap806
24 - description: Armada 7040 SoC
[all …]
/linux/Documentation/hwmon/
H A Dk10temp.rst8 Socket F: Quad-Core/Six-Core/Embedded Opteron (but see below)
10 Socket AM2+: Quad-Core Opteron, Phenom (II) X3/X4, Athlon X2 (but see below)
12 Socket AM3: Quad-Core Opteron, Athlon/Phenom II X2/X3/X4, Sempron II
20 * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
22 * AMD Family 14h processors: "Brazos" (C/E/G/Z-Series)
24 * AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri",
53 BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
69 Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
88 -----------
109 control cooling systems. Tctl is a non-physical temperature on an
[all …]
H A Dcoretemp.rst5 * All Intel Core family
11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
13 - 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
14 - 0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
15 - 0x36 (Cedar Trail Atom)
19 Intel 64 and IA-32 Architectures Software Developer's Manual
27 -----------
30 inside Intel CPUs. This driver can read both the per-core and per-package
31 temperature using the appropriate sensors. The per-package sensor is new;
[all …]
/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 vcm-supply:
42 vcc-drv-supply:
[all …]
H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
38 vcm-supply:
40 Common-mode voltage regulator.
[all …]
/linux/Documentation/infiniband/
H A Dopa_vnic.rst2 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC)
5 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC) feature
6 supports Ethernet functionality over Omni-Path fabric by encapsulating
11 The patterns of exchanges of Omni-Path encapsulated Ethernet packets
12 involves one or more virtual Ethernet switches overlaid on the Omni-Path
13 fabric topology. A subset of HFI nodes on the Omni-Path fabric are
26 +-------------------+
30 +-------------------+
35 +-----------------------------+ +------------------------------+
37 | +---------+ +---------+ | | +---------+ +---------+ |
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dqcom,spi-qcom-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 dual, or quad wire transmission modes for read/write access to slaves such
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
23 - qcom,sc7180-qspi
[all …]
H A Dnvidia,tegra210-quad-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral properties for Tegra Quad SPI Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 nvidia,tx-clk-tap-delay:
23 nvidia,rx-clk-tap-delay:
H A Dnvidia,tegra210-quad.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Quad SPI Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra210-qspi
17 - nvidia,tegra186-qspi
18 - nvidia,tegra194-qspi
[all …]
H A Dqcom,spi-qpic-snand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md sadre Alam <quic_mdalam@quicinc.com>
13 The QCOM QPIC-SPI-NAND flash controller is an extended version of
15 and parallel mode. It supports typical SPI-NAND page cache
16 operations in single, dual or quad IO mode with pipelined ECC
20 - $ref: /schemas/spi/spi-controller.yaml#
25 - items:
[all …]
/linux/arch/arm64/crypto/
H A Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
59 ld1 {v25.8b-v28.8b}, [x1], #32
60 ld1 {v29.8b-v31.8b}, [x1], #24
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dadi,adau1977.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADAU1977/ADAU1978/ADAU1979 Quad ADC with Diagnostics
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Bogdan Togorean <bogdan.togorean@analog.com>
14 Analog Devices ADAU1977 and similar quad ADC with Diagnostics
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1977.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1978.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1979.pdf
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
[all …]
/linux/arch/x86/events/intel/
H A Duncore_snb.c1 // SPDX-License-Identifier: GPL-2.0
162 #define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1)
181 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1)
190 #define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1)
248 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
249 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
250 DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11");
253 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
254 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
255 DEFINE_UNCORE_FORMAT_ATTR(threshold, threshold, "config:24-29");
[all …]
/linux/drivers/mtd/spi-nor/
H A Dgigadevice.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
9 #include "core.h"
18 * the Quad Enable methods. Overwrite the default Quad Enable method. in gd25q256_post_bfpt()
25 if (bfpt_header->major == SFDP_JESD216_MAJOR && in gd25q256_post_bfpt()
26 bfpt_header->minor == SFDP_JESD216_MINOR) in gd25q256_post_bfpt()
27 nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; in gd25q256_post_bfpt()
/linux/include/linux/mtd/
H A Dspi-nor.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #include <linux/spi/spi-mem.h>
18 * requires a 4-byte (32-bit) address.
32 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
33 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
37 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
38 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
53 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
58 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
59 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
[all …]
/linux/drivers/iio/dac/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
28 The driver requires the assistance of an IP core to operate,
33 module will be called ad3552r-hs.
52 tristate "Analog Devices AD5064 and similar multi-channel DAC driver"
56 AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R, AD5627, AD5627R,
70 AD5362, AD5363, AD5370, AD5371, AD5373 multi-channel
83 AD5382, AD5383, AD5384, AD5390, AD5391, AD5392 multi-channel
93 Say yes here to build support for Analog Devices AD5421 loop-powered
94 digital-to-analog converters (DAC).
172 Say yes here to build support for Analog Devices AD9739A Digital-to
[all …]
/linux/Documentation/devicetree/bindings/fpga/
H A Dintel,stratix10-soc-fpga-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mahesh Rao <mahesh.rao@altera.com>
11 - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
12 - Niravkumar L Rabara <nirav.rabara@altera.com>
15 The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 hard
18 on the die.The driver communicates with SDM/ATF via the stratix10-svc
24 - intel,stratix10-soc-fpga-mgr
[all …]
/linux/Documentation/devicetree/bindings/arc/
H A Dhsdk.txt2 ---------------------------------------------------------------------------
4 ARC HSDK Board with quad-core ARC HS38x4 in silicon.
7 - compatible = "snps,hsdk";
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62d2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Device Tree Source for AM62D2 SoC family in Quad core configuration
7 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
10 /dts-v1/;
12 #include "k3-am62a7.dtsi"
19 /delete-node/ &vpu; /* Video Codec is disabled in AM62D2 SoC */
20 /delete-node/ &e5010; /* JPEG Encoder is disabled in AM62D2 SoC */
/linux/Documentation/arch/arm/sti/
H A Dstih418-overview.rst6 ------------
8 The STiH418 is the new generation of SoC for UHDp60 set-top boxes
10 and IP-STB markets.
13 - ARM Cortex-A9 1.5 GHz quad core CPU (28nm)
14 - SATA2, USB 3.0, PCIe, Gbit Ethernet
15 - HEVC L5.1 Main 10
16 - VP9
19 ---------------

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