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/linux/drivers/spi/
H A Dspi-stm32-qspi.c131 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; in stm32_qspi_irq() local
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
141 complete(&qspi->match_completion); in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
150 complete(&qspi->data_completion); in stm32_qspi_irq()
166 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, in stm32_qspi_tx_poll() argument
184 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
188 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", in stm32_qspi_tx_poll()
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H A Dspi-bcm-qspi.c25 #include "spi-bcm-qspi.h"
255 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
257 return qspi->bspi_mode; in has_bspi()
261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
263 if (!has_bspi(qspi) && in bcm_qspi_has_fastbr()
264 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_fastbr()
265 (qspi->mspi_min_rev >= 5))) in bcm_qspi_has_fastbr()
272 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) in bcm_qspi_has_sysclk_108() argument
274 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk || in bcm_qspi_has_sysclk_108()
275 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_sysclk_108()
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H A Dspi-ti-qspi.c3 * TI QSPI driver
126 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
129 return readl(qspi->base + reg); in ti_qspi_read()
132 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
135 writel(val, qspi->base + reg); in ti_qspi_write()
140 struct ti_qspi *qspi = spi_controller_get_devdata(spi->controller); in ti_qspi_setup() local
144 dev_dbg(qspi->dev, "host busy doing other transfers\n"); in ti_qspi_setup()
148 if (!qspi->host->max_speed_hz) { in ti_qspi_setup()
149 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
153 spi->max_speed_hz = min(spi->max_speed_hz, qspi->host->max_speed_hz); in ti_qspi_setup()
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H A Dspi-zynqmp-gqspi.c3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
25 /* Generic QSPI register offsets */
160 * struct qspi_platform_data - zynqmp qspi platform data structure
168 * struct zynqmp_qspi - Defines qspi driver instance
170 * @regs: Virtual address of the QSPI controller registers
184 * @mode: Defines the mode in which QSPI is operating
188 * @has_tapdelay: Used for tapdelay register available in qspi
284 * zynqmp_qspi_set_tapdelay: To configure qspi tap delays
337 * The default settings of the QSPI controller's configurable parameters on
351 * - Enable the QSPI controller
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/linux/Documentation/devicetree/bindings/spi/
H A Dfsl,spi-fsl-qspi.yaml4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
21 - fsl,imx7d-qspi
22 - fsl,imx6ul-qspi
23 - fsl,ls1021a-qspi
24 - fsl,ls2080a-qspi
27 - fsl,ls1043a-qspi
28 - const: fsl,ls1021a-qspi
31 - fsl,imx8mq-qspi
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H A Drenesas,rspi.yaml7 title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI)
31 - renesas,qspi-r8a7742 # RZ/G1H
32 - renesas,qspi-r8a7743 # RZ/G1M
33 - renesas,qspi-r8a7744 # RZ/G1N
34 - renesas,qspi-r8a7745 # RZ/G1E
35 - renesas,qspi-r8a77470 # RZ/G1C
36 - renesas,qspi-r8a7790 # R-Car H2
37 - renesas,qspi-r8a7791 # R-Car M2-W
38 - renesas,qspi-r8a7792 # R-Car V2H
39 - renesas,qspi-r8a7793 # R-Car M2-N
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H A Dqcom,spi-qcom-qspi.yaml4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
12 description: The QSPI controller allows SPI protocol communication in single,
23 - qcom,sc7180-qspi
24 - qcom,sc7280-qspi
25 - qcom,sdm845-qspi
27 - const: qcom,qspi-v1
46 - description: QSPI core clock
55 - const: qspi-config
56 - const: qspi-memory
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H A Dbrcm,spi-bcm-qspi.yaml4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
36 - brcm,spi-bcm7425-qspi
37 - brcm,spi-bcm7429-qspi
38 - brcm,spi-bcm7435-qspi
39 - brcm,spi-bcm7445-qspi
40 - brcm,spi-bcm7216-qspi
41 - brcm,spi-bcm7278-qspi
42 - const: brcm,spi-bcm-qspi
47 - brcm,spi-brcmstb-qspi
49 - brcm,spi-nsp-qspi
[all …]
H A Dnvidia,tegra210-quad.yaml16 - nvidia,tegra210-qspi
17 - nvidia,tegra186-qspi
18 - nvidia,tegra194-qspi
19 - nvidia,tegra234-qspi
20 - nvidia,tegra241-qspi
30 - const: qspi
79 const: nvidia,tegra234-qspi
90 compatible = "nvidia,tegra210-qspi";
97 clock-names = "qspi", "qspi_out";
H A Dti,qspi.yaml4 $id: http://devicetree.org/schemas/spi/ti,qspi.yaml#
7 title: TI QSPI controller
18 - ti,am4372-qspi
19 - ti,dra7xxx-qspi
48 Name of the hwmod associated to the QSPI. This is for legacy
55 Handle to system control region containing QSPI chipselect register
83 compatible = "ti,dra7xxx-qspi";
H A Dspi-zynqmp-qspi.yaml4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
15 - xlnx,versal-qspi-1.0
16 - xlnx,zynqmp-qspi-1.0
55 const: xlnx,zynqmp-qspi-1.0
72 qspi: spi@ff0f0000 {
73 compatible = "xlnx,zynqmp-qspi-1.0";
H A Dst,stm32-qspi.yaml4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
7 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI)
18 const: st,stm32f469-qspi
27 - const: qspi
68 compatible = "st,stm32f469-qspi";
70 reg-names = "qspi", "qspi_mm";
H A Dxlnx,zynq-qspi.yaml4 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
22 const: xlnx,zynq-qspi-1.0
52 compatible = "xlnx,zynq-qspi-1.0";
H A Dmicrochip,mpfs-spi.yaml10 SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
21 - microchip,mpfs-qspi
22 - microchip,pic64gx-qspi
24 - const: microchip,coreqspi-rtl-v2 # FPGA QSPI
H A Dcdns,qspi-nor-peripheral-props.yaml4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
16 # cdns,qspi-nor.yaml
/linux/arch/m68k/include/asm/
H A Dmcfqspi.h3 * Definitions for Freescale Coldfire QSPI module
12 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
18 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
20 * platform data for each QSPI master controller. Only the select and
31 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
32 * @bus_num: board specific identifier for this qspi driver.
33 * @num_chipselects: number of chip selects supported by this qspi driver.
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-cc108.dts21 spi0 = &qspi;
55 &qspi {
67 label = "qspi-fsbl-uboot-bs";
71 label = "qspi-linux";
75 label = "qspi-rootfs";
79 label = "qspi-devicetree";
83 label = "qspi-scratch";
87 label = "qspi-uboot-env";
H A Dzynq-zed.dts16 spi0 = &qspi;
50 &qspi {
66 label = "qspi-fsbl-uboot";
70 label = "qspi-linux";
74 label = "qspi-device-tree";
78 label = "qspi-rootfs";
82 label = "qspi-bitstream";
H A Dzynq-zc770-xm013.dts18 spi0 = &qspi;
61 &qspi {
76 label = "qspi-fsbl-uboot";
80 label = "qspi-linux";
84 label = "qspi-device-tree";
88 label = "qspi-rootfs";
92 label = "qspi-bitstream";
H A Dzynq-zc770-xm010.dts18 spi0 = &qspi;
62 &qspi {
76 label = "qspi-fsbl-uboot";
80 label = "qspi-linux";
84 label = "qspi-device-tree";
88 label = "qspi-rootfs";
92 label = "qspi-bitstream";
H A Dzynq-zc706.dts17 spi0 = &qspi;
308 &qspi {
324 label = "qspi-fsbl-uboot";
328 label = "qspi-linux";
332 label = "qspi-device-tree";
336 label = "qspi-rootfs";
340 label = "qspi-bitstream";
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-evm-common.dtsi134 &qspi {
153 label = "QSPI.SPL";
157 label = "QSPI.SPL.backup1";
161 label = "QSPI.SPL.backup2";
165 label = "QSPI.SPL.backup3";
169 label = "QSPI.u-boot";
173 label = "QSPI.u-boot-spl-os";
177 label = "QSPI.u-boot-env";
181 label = "QSPI.u-boot-env.backup1";
185 label = "QSPI.kernel";
[all …]
H A Ddra72-evm-common.dtsi473 &qspi {
492 label = "QSPI.SPL";
496 label = "QSPI.SPL.backup1";
500 label = "QSPI.SPL.backup2";
504 label = "QSPI.SPL.backup3";
508 label = "QSPI.u-boot";
512 label = "QSPI.u-boot-spl-os";
516 label = "QSPI.u-boot-env";
520 label = "QSPI.u-boot-env.backup1";
524 label = "QSPI.kernel";
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/linux/drivers/pinctrl/
H A Dpinctrl-th1520.c120 [TH1520_MUX_QSPI] = "qspi",
216 TH1520_PAD(0, QSPI1_SCLK, QSPI, ISO, ____, GPIO, FUSE, ____, 0),
217 TH1520_PAD(1, QSPI1_CSN0, QSPI, ____, I2C, GPIO, FUSE, ____, 0),
218 TH1520_PAD(2, QSPI1_D0_MOSI, QSPI, ISO, I2C, GPIO, FUSE, ____, 0),
219 TH1520_PAD(3, QSPI1_D1_MISO, QSPI, ISO, ____, GPIO, FUSE, ____, 0),
220 TH1520_PAD(4, QSPI1_D2_WP, QSPI, ISO, UART, GPIO, FUSE, ____, 0),
221 TH1520_PAD(5, QSPI1_D3_HOLD, QSPI, ISO, UART, GPIO, ____, ____, 0),
240 TH1520_PAD(24, GPIO0_24, GPIO, JTAG, QSPI, ____, DPU0, DPU1, 0),
254 TH1520_PAD(38, GPIO1_6, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
255 TH1520_PAD(39, GPIO1_7, GPIO, QSPI, ____, ____, DPU0, DPU1, 0),
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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_socdk_qspi.dts9 &qspi {
26 partition@qspi-boot {
31 partition@qspi-rootfs {

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