Searched +full:qoriq +full:- +full:core +full:- +full:pll +full:- +full:1 (Results 1 – 6 of 6) sorted by relevance
/linux/Documentation/devicetree/bindings/clock/ |
H A D | fsl,qoriq-clock-legacy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Legacy Clock Block on Freescale QorIQ Platforms 10 - Frank Li <Frank.Li@nxp.com> 16 Most of the bindings are from the common clock binding[1]. 17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 22 - fsl,qoriq-core-pll-1.0 23 - fsl,qoriq-core-pll-2.0 [all …]
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H A D | fsl,qoriq-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Clock Block on Freescale QorIQ Platforms 10 - Frank Li <Frank.Li@nxp.com> 13 Freescale QorIQ chips take primary clocking input from the external 15 multiple phase locked loops (PLL) to create a variety of frequencies 20 All references to "1.0" and "2.0" refer to the QorIQ chassis version to 24 --------------- ------------- [all …]
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H A D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock 10 - Wen He <wen.he_1@nxp.com> 14 interface in the display core, as implemented in TSMC CLN28HPM PLL. 19 const: fsl,ls1028a-plldig 22 maxItems: 1 25 maxItems: 1 27 '#clock-cells': [all …]
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/linux/drivers/clk/ |
H A D | clk-qoriq.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * clock driver for Freescale QorIQ SoCs. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13 #include <linux/clk-provider.h> 25 #define PLL_DIV2 1 30 #define CGA_PLL1 1 33 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */ 47 #define CLKSEL_VALID 1 48 #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */ 52 int pll; /* CGx_PLLn */ member [all …]
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/linux/ |
H A D | MAINTAINERS | 5 --------------------------------------------------- 21 W: *Web-page* with status/info 23 B: URI for where to file *bugs*. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-scsi@vger.kernel.org 88 F: drivers/scsi/3w-* [all …]
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/linux/Documentation/admin-guide/ |
H A D | kernel-parameters.txt | 16 force -- enable ACPI if default was off 17 on -- enable ACPI but allow fallback to DT [arm64,riscv64] 18 off -- disable ACPI if default was on 19 noirq -- do not use ACPI for IRQ routing 20 strict -- Be less tolerant of platforms that are not 22 rsdt -- prefer RSDT over (default) XSDT 23 copy_dsdt -- copy DSDT to memory 24 nospcr -- disable console in ACPI SPCR table as 36 1,0: use 1st APIC table 41 If set to vendor, prefer vendor-specific driver [all …]
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