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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dqe.txt1 * Freescale QUICC Engine module (QE)
2 This represents qe module that is installed on PowerQUICC II Pro.
9 the "root" qe node, using the common properties from there.
10 The description below applies to the qe of MPC8360 and
13 i) Root QE device
16 - compatible : should be "fsl,qe";
17 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18 - reg : offset and length of the device registers.
19 - bus-frequency : the clock frequency for QUICC Engine.
20 - fsl,qe-num-riscs: define how many RISC engines the QE has.
[all …]
H A Dfsl,qe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine module (QE)
10 - Frank Li <Frank.Li@nxp.com>
13 This represents qe module that is installed on PowerQUICC II Pro.
20 the "root" qe node, using the common properties from there.
21 The description below applies to the qe of MPC8360 and
27 - const: fsl,qe
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H A Dfsl,qe-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 property, and any firmware-specific properties. The node should be placed
19 inside a QE node that needs it. Doing so eliminates the need for a
20 fsl,firmware-phandle property. Other QE nodes that need the same firmware
21 should define an fsl,firmware-phandle property that points to the firmware node
22 in the first QE node.
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H A Dfsl,qe-ucc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE QUICC Multichannel Controller (QMC)
10 - Herve Codina <herve.codina@bootlin.com>
19 - enum:
20 - fsl,mpc8321-ucc-qmc
21 - const: fsl,qe-ucc-qmc
25 - description: UCC (Unified communication controller) register base
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H A Dfsl,qe-si.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-si.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The SI manages the routing of eight TDM lines to the QE block serial drivers,
19 - items:
20 - enum:
21 - fsl,ls1043-qe-si
22 - const: fsl,t1040-qe-si
[all …]
H A Dfsl,qe-muram.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-muram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine Multi-User RAM (MURAM)
10 - Frank Li <Frank.Li@nxp.com>
12 description: Multi-User RAM (MURAM)
17 - const: fsl,qe-muram
18 - const: fsl,cpm-muram
23 "#address-cells":
[all …]
H A Dfsl,qe-siram.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-siram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 - items:
19 - enum:
20 - fsl,ls1043-qe-siram
21 - const: fsl,t1040-qe-siram
22 - const: fsl,t1040-qe-siram
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H A Dfsl,qe-ic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
14 const: fsl,qe-ic
21 - description: QE interrupt
22 - description: QE critical
23 - description: QE error
26 interrupt-controller: true
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H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
H A Dcpm.txt4 as more devices are supported. The QE bindings especially are
10 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11 - reg : A 48-byte region beginning with CPCR.
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
22 * Properties common to multiple CPM/QE devices
24 - fsl,cpm-command : This value is ORed with the opcode and command flag
27 - fsl,cpm-brg : Indicates which baud rate generator the device
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc836x_rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2007-2008 MontaVista Software, Inc.
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 compatible = "fsl,mpc8360rdk";
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
[all …]
H A Dmpc836x_mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <32768>; // L1, 32K
39 i-cache-size = <32768>; // L1, 32K
[all …]
H A Dmpc832x_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <16384>; // L1, 16K
34 i-cache-size = <16384>; // L1, 16K
[all …]
H A Dmpc832x_mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
14 * 3) Solder a wire from U61-22 to P19K-22.
18 * you're going by the schematic, the pin is called "P19J-K22".
21 /dts-v1/;
26 #address-cells = <1>;
27 #size-cells = <1>;
38 #address-cells = <1>;
39 #size-cells = <0>;
44 d-cache-line-size = <32>; // 32 bytes
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt1024si-post.dtsi35 #include "t1023si-post.dtsi"
43 qe:qe@ffe140000 { label
44 #address-cells = <1>;
45 #size-cells = <1>;
46 device_type = "qe";
47 compatible = "fsl,qe";
50 fsl,qe-num-riscs = <1>;
51 fsl,qe-num-snums = <28>;
52 brg-frequency = <0>;
53 bus-frequency = <0>;
[all …]
H A Dmpc8569si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
56 #interrupt-cells = <1>;
57 #size-cells = <2>;
[all …]
H A Dp1021si-post.dtsi4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
[all …]
H A Dmpc8568si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
45 compatible = "fsl,mpc8540-pci";
48 bus-range = <0 0xff>;
49 #interrupt-cells = <1>;
50 #size-cells = <2>;
51 #address-cells = <3>;
57 compatible = "fsl,mpc8548-pcie";
59 #size-cells = <2>;
[all …]
H A Dmpc8569mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8569si-pre.dtsi"
12 compatible = "fsl,MPC8569EMDS";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&mpic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
44 bank-width = <1>;
[all …]
H A Dt104xd4rdb.dtsi36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
41 bman_fbpr: bman-fbpr {
45 qman_fqd: qman-fqd {
49 qman_pfdr: qman-pfdr {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
66 bank-width = <2>;
[all …]
H A Dt104xrdb.dtsi4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
42 reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
47 bman_fbpr: bman-fbpr {
51 qman_fqd: qman-fqd {
55 qman_pfdr: qman-pfdr {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "cfi-flash";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dfsl,gtm.txt1 * Freescale General-purpose Timers Module
4 - compatible : should be
5 "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
6 "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
7 "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
8 - reg : should contain gtm registers location and length (0x40).
9 - interrupts : should contain four interrupts.
10 - clock-frequency : specifies the frequency driving the timer.
15 compatible = "fsl,mpc8360-gtm", "fsl,gtm";
18 interrupt-parent = <&ipic>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/qe/
H A Dpar_io.txt3 This node configures Parallel I/O ports for CPUs with QE support.
10 - device_type : should be "par_io".
11 - reg : offset to the register set and its length.
12 - num-ports : number of Parallel I/O ports
17 #address-cells = <1>;
18 #size-cells = <0>;
20 num-ports = <7>;
27 via its own gpio-controller node:
30 - #gpio-cells : should be "2".
31 - compatible : should be "fsl,<chip>-qe-pario-bank",
[all …]
H A Dusb.txt4 - compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
5 - reg : the first two cells should contain usb registers location and
8 - interrupts : should contain USB interrupt.
9 - fsl,fullspeed-clock : specifies the full speed USB clock source:
11 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
12 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
13 - fsl,lowspeed-clock : specifies the low speed USB clock source:
15 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
16 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
17 - hub-power-budget : USB power budget for the root hub, in mA.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dfsl-spi.txt4 - cell-index : QE SPI subblock index.
5 0: QE subblock SPI1
6 1: QE subblock SPI2
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - cs-gpios : specifies the gpio pins to be used for chipselects.
21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
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