| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/ |
| H A D | qe.txt | 1 * Freescale QUICC Engine module (QE)
2 This represents qe module that is installed on PowerQUICC II Pro.
9 the "root" qe node, using the common properties from there.
10 The description below applies to the qe of MPC8360 and
13 i) Root QE device
16 - compatible : should be "fsl,qe";
17 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18 - reg : offset and length of the device registers.
19 - bus-frequency : the clock frequency for QUICC Engine.
20 - fsl,qe-num-riscs: define how many RISC engines the QE has.
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| H A D | fsl,qe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine module (QE)
10 - Frank Li <Frank.Li@nxp.com>
13 This represents qe module that is installed on PowerQUICC II Pro.
20 the "root" qe node, using the common properties from there.
21 The description below applies to the qe of MPC8360 and
27 - const: fsl,qe
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| H A D | fsl,qe-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine module Firmware Node
10 - Frank Li <Frank.Li@nxp.com>
13 This node defines a firmware binary that is embedded in the device tree, for
14 the purpose of passing the firmware from bootloader to the kernel, or from
17 The firmware node itself contains the firmware binary contents, a compatible
18 property, and any firmware-specific properties. The node should be placed
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| H A D | fsl,qe-ucc-qmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE QUICC Multichannel Controller (QMC)
10 - Herve Codina <herve.codina@bootlin.com>
19 - enum:
20 - fsl,mpc8321-ucc-qmc
21 - const: fsl,qe-ucc-qmc
25 - description: UCC (Unified communication controller) register base
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| /freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/qe/ |
| H A D | firmware.txt | 1 * Uploaded QE firmware
3 If a new firmware has been uploaded to the QE (usually by the
4 boot loader), then a 'firmware' child node should be added to the QE
5 node. This node provides information on the uploaded firmware that
9 - id: The string name of the firmware. This is taken from the 'id'
10 member of the qe_firmware structure of the uploaded firmware.
12 firmware they want is already present.
13 - extended-modes: The Extended Modes bitfield, taken from the
14 firmware binary. It is a 64-bit number represented
15 as an array of two 32-bit numbers.
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| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | p1025twr.dtsi | 2 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
48 bank-width = <2>;
49 device-width = <1>;
53 /* 256KB for Vitesse 7385 Switch firmware */
55 label = "NOR Vitesse-7385 Firmware";
56 read-only;
79 /* 256KB for QE ucode firmware*/
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| H A D | p1021rdb-pc.dtsi | 2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 /* 256KB for Vitesse 7385 Switch firmware */
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 256KB for QE ucode firmware*/
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| H A D | p1025rdb_36b.dts | 2 * P1025 RDB Device Tree Source (36-bit address map)
35 /include/ "p1021si-pre.dtsi"
86 qe: qe@fffe80000 { label
87 status = "disabled"; /* no firmware loaded */
93 /include/ "p1021si-post.dtsi"
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| H A D | p1025rdb_32b.dts | 2 * P1025 RDB Device Tree Source (32-bit address map)
35 /include/ "p1021si-pre.dtsi"
86 qe: qe@ffe80000 { label
89 brg-frequency = <0>;
90 bus-frequency = <0>;
91 status = "disabled"; /* no firmware loaded */
96 rx-clock-name = "clk12";
97 tx-clock-name = "clk9";
98 pio-handle = <&pio1>;
99 phy-handle = <&qe_phy0>;
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| H A D | mpc8569mds.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8569si-pre.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&mpic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
44 bank-width = <1>;
45 device-width = <1>;
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| H A D | p1021mds.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "p1021si-pre.dtsi"
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "fsl,p1021-fcm-nand",
35 "fsl,elbc-fcm-nand";
40 /* 1MB for u-boot Bootloader Image */
42 label = "NAND (RO) U-Boot Image";
43 read-only;
50 read-only;
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| H A D | p1025rdb.dtsi | 2 * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 /* 256KB for Vitesse 7385 Switch firmware */
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
72 /* 512KB for u-boot Bootloader Image */
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | fsl-ls1043a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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| /freebsd/sys/dev/isp/ |
| H A D | ispvar.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2020 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 1997-2009 by Matthew Jacob
84 * Macros to access ISP registers through bus specific layers-
88 (*(isp)->isp_mdvec->dv_run_isr)(isp)
91 (*(isp)->isp_mdvec->dv_rd_reg)((isp), (reg))
94 (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val))
97 (*(isp)->isp_mdvec->dv_mbxdma)((isp))
99 #define ISP_SEND_CMD(isp, qe, segp, nseg) \ argument
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| H A D | isp.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2020 Alexander Motin <mav@FreeBSD.org>
5 * Copyright (c) 1997-2009 by Matthew Jacob
34 * code for the Qlogic ISP SCSI and FC-SCSI adapters.
54 #include <sys/firmware.h>
151 if (fcp->isp_fwstat in isp_change_fw_state()
3289 uint8_t qe[QENTRY_LEN]; isp_intr_respq() local
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| /freebsd/sys/dev/ocs_fc/ |
| H A D | sli4.c | 1 /*-
33 * @defgroup sli SLI-4 Base APIs
38 * All common (i.e. transport-independent) SLI-4 functions are implemented
113 * Although SLI-4 specification defines a common set of registers, their locations
260 const sli4_reg_t *r = &(regmap[reg][sli->if_type]); in sli_reg_read()
262 if ((UINT32_MAX == r->rset) || (UINT32_MAX == r->off)) { in sli_reg_read()
263 ocs_log_err(sli->os, "regname %d not defined for if_type %d\n", reg, sli->if_type); in sli_reg_read()
267 return ocs_reg_read32(sli->os, r->rset, r->off); in sli_reg_read()
282 const sli4_reg_t *r = &(regmap[reg][sli->if_type]); in sli_reg_write()
284 if ((UINT32_MAX == r->rset) || (UINT32_MAX == r->off)) { in sli_reg_write()
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