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Searched +full:qdma +full:- +full:error (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/dma/
H A Dfsl-qdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Layerscape SoC qDMA Controller
10 - Frank Li <Frank.Li@nxp.com>
15 - const: fsl,ls1021a-qdma
16 - items:
17 - enum:
18 - fsl,ls1028a-qdma
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/linux/drivers/dma/
H A Dfsl-qdma.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2014-2015 Freescale
18 #include <linux/dma-mapping.h>
21 #include "virt-dma.h"
137 (((fsl_qdma_engine)->block_offset) * (x))
140 * struct fsl_qdma_format - This is the struct holding describing compound
141 * descriptor format with qDMA.
145 * 32-bits address in memory 40-bit address.
146 * @addr_hi: Same as above member, but point high 8-bits in
147 * memory 40-bit address.
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/linux/drivers/net/ethernet/airoha/
H A Dairoha_eth.c1 // SPDX-License-Identifier: GPL-2.0-only
41 struct airoha_qdma *qdma = irq_bank->qdma; in airoha_qdma_set_irqmask() local
42 int bank = irq_bank - &qdma->irq_banks[0]; in airoha_qdma_set_irqmask()
45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask))) in airoha_qdma_set_irqmask()
48 spin_lock_irqsave(&irq_bank->irq_lock, flags); in airoha_qdma_set_irqmask()
50 irq_bank->irqmask[index] &= ~clear; in airoha_qdma_set_irqmask()
51 irq_bank->irqmask[index] |= set; in airoha_qdma_set_irqmask()
52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), in airoha_qdma_set_irqmask()
53 irq_bank->irqmask[index]); in airoha_qdma_set_irqmask()
57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); in airoha_qdma_set_irqmask()
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/linux/drivers/pci/controller/
H A Dpcie-xilinx-dma-pl.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/irqchip/irq-msi-lib.h>
19 #include "pcie-xilinx-common.h"
62 /* Root Port Error Register definitions */
82 QDMA, enumerator
86 * struct xilinx_pl_dma_variant - PL DMA PCIe variant information
102 * struct pl_dma_pcie - PCIe port information
113 * @intx_irq: INTx error interrupt number
135 if (port->variant->version == QDMA) in pcie_read()
136 return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); in pcie_read()
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/linux/drivers/dma/amd/qdma/
H A Dqdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for AMD Queue-based DMA Subsystem
5 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
10 #include <linux/dma-mapping.h>
17 #include "qdma.h"
19 #define CHAN_STR(q) (((q)->dir == DMA_MEM_TO_DEV) ? "H2C" : "C2H")
20 #define QDMA_REG_OFF(d, r) ((d)->roffs[r].off)
22 /* MMIO regmap config for all QDMA registers */
43 idx = qdev->qintr_rings[qdev->qintr_ring_idx++].ridx; in qdma_get_intr_ring_idx()
44 qdev->qintr_ring_idx %= qdev->qintr_ring_num; in qdma_get_intr_ring_idx()
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/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
35 static int mtk_msg_level = -1;
37 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
61 .qdma = {
127 .qdma = {
178 .qdma = {
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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/linux/drivers/dma/fsl-dpaa2-qdma/
H A Ddpdmai.c1 // SPDX-License-Identifier: GPL-2.0
52 * dpdmai_open() - Open a control session for the specified object
66 * Return: '0' on Success; Error code otherwise.
80 cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id); in dpdmai_open()
95 * dpdmai_close() - Close the control session of the object
103 * Return: '0' on Success; Error code otherwise.
119 * dpdmai_destroy() - Destroy the DPDMAI object and release all its resources.
125 * Return: '0' on Success; error code otherwise.
137 cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id); in dpdmai_destroy()
145 * dpdmai_enable() - Enable the DPDMAI, allow sending and receiving frames.
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/linux/drivers/usb/mtu3/
H A Dmtu3_qmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * mtu3_qmu.c - Queue Management Unit driver for device controller
34 #define GET_GPD_HWO(gpd) (le32_to_cpu((gpd)->dw0_info) & GPD_FLAGS_HWO)
41 ((mtu)->gen2cp) ? GPD_RX_BUF_LEN_EL(x_) : GPD_RX_BUF_LEN_OG(x_); \
49 ((mtu)->gen2cp) ? GPD_DATA_LEN_EL(x_) : GPD_DATA_LEN_OG(x_); \
60 ((mtu)->gen2cp) ? GPD_EXT_NGP_EL(x_) : GPD_EXT_NGP_OG(x_); \
66 ((mtu)->gen2cp) ? GPD_EXT_BUF_EL(x_) : GPD_EXT_BUF_OG(x_); \
122 dma_addr_t dma_base = ring->dma; in gpd_dma_to_virt()
123 struct qmu_gpd *gpd_head = ring->start; in gpd_dma_to_virt()
124 u32 offset = (dma_addr - dma_base) / sizeof(*gpd_head); in gpd_dma_to_virt()
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/linux/include/uapi/linux/
H A Dhdreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
139 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
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/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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