| /linux/drivers/net/ethernet/airoha/ |
| H A D | airoha_eth.c | 41 struct airoha_qdma *qdma = irq_bank->qdma; in airoha_qdma_set_irqmask() local
42 int bank = irq_bank - &qdma->irq_banks[0]; in airoha_qdma_set_irqmask()
52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), in airoha_qdma_set_irqmask()
57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); in airoha_qdma_set_irqmask()
76 struct airoha_eth *eth = port->qdma->eth; in airoha_set_macaddr()
107 struct airoha_eth *eth = port->qdma->eth; in airoha_set_vip_for_gdm_port()
504 /* QDMA LAN, RX Ring-22 */ in airoha_fe_init()
555 struct airoha_qdma *qdma = q->qdma; in airoha_qdma_fill_rx_queue() local
556 struct airoha_eth *eth = qdma->eth; in airoha_qdma_fill_rx_queue()
557 int qid = q - &qdma->q_rx[0]; in airoha_qdma_fill_rx_queue()
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| H A D | airoha_eth.h | 177 struct airoha_qdma *qdma; member
197 struct airoha_qdma *qdma; member
496 struct airoha_qdma *qdma; member
519 struct airoha_qdma *qdma; member
570 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; member
589 #define airoha_qdma_rr(qdma, offset) \ argument
590 airoha_rr((qdma)->regs, (offset))
591 #define airoha_qdma_wr(qdma, offset, val) \ argument
592 airoha_wr((qdma)->regs, (offset), (val))
593 #define airoha_qdma_rmw(qdma, offset, mask, val) \ argument
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| H A D | airoha_ppe.c | 875 struct airoha_eth *eth = port->qdma->eth; in airoha_ppe_flow_offload_replace()
1070 struct airoha_eth *eth = port->qdma->eth; in airoha_ppe_flow_offload_destroy()
1116 struct airoha_eth *eth = port->qdma->eth; in airoha_ppe_flow_offload_stats()
1220 struct airoha_eth *eth = port->qdma->eth; in airoha_ppe_setup_tc_block_cb()
1254 struct airoha_eth *eth = port->qdma->eth; in airoha_ppe_init_upd_mem()
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | fsl-qdma.yaml | 4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
7 title: NXP Layerscape SoC qDMA Controller
15 - const: fsl,ls1021a-qdma
18 - fsl,ls1028a-qdma
19 - fsl,ls1043a-qdma
20 - fsl,ls1046a-qdma
21 - const: fsl,ls1021a-qdma
36 - const: qdma-error
37 - const: qdma-queue0
38 - const: qdma-queue1
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| /linux/drivers/dma/amd/qdma/ |
| H A D | Makefile | 3 obj-$(CONFIG_AMD_QDMA) += amd-qdma.o
5 amd-qdma-$(CONFIG_AMD_QDMA) := qdma.o qdma-comm-regs.o
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| H A D | qdma.c | 17 #include "qdma.h"
22 /* MMIO regmap config for all QDMA registers */
934 IRQF_ONESHOT, "amd-qdma-error", qdev); in qdma_init_error_irq()
1000 "amd-qdma-queue", ring); in qdmam_alloc_qintr_rings()
1117 qdma_err(qdev, "Failed to register AMD QDMA: %d", ret); in amd_qdma_probe()
1127 qdma_err(qdev, "Failed to probe AMD QDMA driver"); in amd_qdma_probe()
1133 .name = "amd-qdma",
1141 MODULE_DESCRIPTION("AMD QDMA driver");
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| H A D | qdma-comm-regs.c | 9 #include "qdma.h"
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| H A D | qdma.h | 24 #define QDMA_INTR_PREFIX "amd-qdma"
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| /linux/drivers/net/ethernet/mediatek/ |
| H A D | mtk_eth_soc.h | 244 /* QDMA TX Queue Configuration Registers */
248 /* QDMA Tx Queue Scheduler Configuration Registers */
262 /* QDMA TX Scheduler Rate Control Register */
265 /* QDMA Global Configuration Register */
277 /* QDMA V2 Global Configuration Register */
285 /* QDMA Flow Control Register */
290 /* QDMA Interrupt Status Register */
308 /* QDMA Interrupt grouping registers */
311 /* QDMA TX NUM */
317 /* QDMA V2 descriptor txd6 */
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| H A D | mtk_eth_soc.c | 60 .qdma = {
126 .qdma = {
177 .qdma = {
806 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); in mtk_set_queue_speed()
1270 /* the qdma core needs scratch memory to be setup */
1329 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); in mtk_init_fq_dma()
1330 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); in mtk_init_fq_dma()
1331 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); in mtk_init_fq_dma()
1332 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); in mtk_init_fq_dma()
1659 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); in mtk_tx_map()
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| /linux/drivers/dma/fsl-dpaa2-qdma/ |
| H A D | Makefile | 2 # Makefile for the NXP DPAA2 qDMA controllers
3 obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o
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| H A D | Kconfig | 2 tristate "NXP DPAA2 QDMA"
8 NXP Data Path Acceleration Architecture 2 QDMA driver,
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| H A D | dpaa2-qdma.h | 71 struct dpaa2_qdma_engine *qdma; member
77 /* spinlock used by dpaa2 qdma driver */
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | xlnx,xdma-host.yaml | 19 - xlnx,qdma-host-3.00
24 - description: QDMA bridge register.
95 - xlnx,qdma-host-3.00
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| /linux/drivers/pci/controller/ |
| H A D | pcie-xilinx-dma-pl.c | 81 QDMA, enumerator
135 if (port->variant->version == QDMA) in pcie_read()
143 if (port->variant->version == QDMA) in pcie_write()
200 if (port->variant->version == QDMA) in xilinx_pl_dma_pcie_map_bus()
754 if (port->variant->version == QDMA) { in xilinx_pl_dma_pcie_parse_dt()
830 .version = QDMA,
839 .compatible = "xlnx,qdma-host-3.00",
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls1043a.dtsi | 957 qdma: dma-controller@8380000 { label
958 compatible = "fsl,ls1043a-qdma", "fsl,ls1021a-qdma";
967 interrupt-names = "qdma-error", "qdma-queue0",
968 "qdma-queue1", "qdma-queue2", "qdma-queue3";
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| H A D | fsl-ls1046a.dtsi | 913 qdma: dma-controller@8380000 { label
914 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
923 interrupt-names = "qdma-error", "qdma-queue0",
924 "qdma-queue1", "qdma-queue2", "qdma-queue3";
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| H A D | fsl-ls1028a.dtsi | 816 qdma: dma-controller@8380000 { label
817 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
826 interrupt-names = "qdma-error", "qdma-queue0",
827 "qdma-queue1", "qdma-queue2", "qdma-queue3";
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| /linux/drivers/dma/ |
| H A D | Makefile | 41 obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
85 obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
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| H A D | Kconfig | 231 tristate "NXP Layerscape qDMA engine support"
238 Support the NXP Layerscape qDMA engine with command queue and legacy mode.
242 The qdma driver only work on SoCs with a DPAA hardware block.
765 source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
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| /linux/include/linux/platform_data/ |
| H A D | amd_qdma.h | 25 * struct qdma_platdata - Platform specific data for QDMA engine
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| H A D | edma.h | 33 * DaVinci hardware also has a "QDMA" mechanism which is not currently
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| /linux/drivers/net/ethernet/sfc/ |
| H A D | ef100_ethtool.c | 20 /* This is the maximum number of descriptor rings supported by the QDMA */
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| /linux/arch/arm/boot/dts/nxp/ls/ |
| H A D | ls1021a.dtsi | 920 qdma: dma-controller@8390000 { label
921 compatible = "fsl,ls1021a-qdma";
928 interrupt-names = "qdma-error",
929 "qdma-queue0", "qdma-queue1";
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| /linux/include/uapi/linux/ |
| H A D | hdreg.h | 335 #define HDIO_GET_QDMA 0x0305 /* get use-qdma flag */
374 #define HDIO_SET_QDMA 0x032e /* change use-qdma flag */
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