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Searched full:qdma (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/net/ethernet/airoha/
H A Dairoha_eth.c41 struct airoha_qdma *qdma = irq_bank->qdma; in airoha_qdma_set_irqmask() local
42 int bank = irq_bank - &qdma->irq_banks[0]; in airoha_qdma_set_irqmask()
52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), in airoha_qdma_set_irqmask()
57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); in airoha_qdma_set_irqmask()
76 struct airoha_eth *eth = port->qdma->eth; in airoha_set_macaddr()
107 struct airoha_eth *eth = port->qdma->eth; in airoha_set_vip_for_gdm_port()
504 /* QDMA LAN, RX Ring-22 */ in airoha_fe_init()
554 struct airoha_qdma *qdma = q->qdma; in airoha_qdma_fill_rx_queue() local
555 int qid = q - &qdma->q_rx[0]; in airoha_qdma_fill_rx_queue()
588 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), in airoha_qdma_fill_rx_queue()
[all …]
H A Dairoha_regs.h399 /* QDMA */
/linux/Documentation/devicetree/bindings/dma/
H A Dfsl-qdma.yaml4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
7 title: NXP Layerscape SoC qDMA Controller
15 - const: fsl,ls1021a-qdma
18 - fsl,ls1028a-qdma
19 - fsl,ls1043a-qdma
20 - fsl,ls1046a-qdma
21 - const: fsl,ls1021a-qdma
36 - const: qdma-error
37 - const: qdma-queue0
38 - const: qdma-queue1
[all …]
/linux/drivers/dma/amd/qdma/
H A DMakefile3 obj-$(CONFIG_AMD_QDMA) += amd-qdma.o
5 amd-qdma-$(CONFIG_AMD_QDMA) := qdma.o qdma-comm-regs.o
H A Dqdma.c17 #include "qdma.h"
22 /* MMIO regmap config for all QDMA registers */
934 IRQF_ONESHOT, "amd-qdma-error", qdev); in qdma_init_error_irq()
1000 "amd-qdma-queue", ring); in qdmam_alloc_qintr_rings()
1117 qdma_err(qdev, "Failed to register AMD QDMA: %d", ret); in amd_qdma_probe()
1127 qdma_err(qdev, "Failed to probe AMD QDMA driver"); in amd_qdma_probe()
1133 .name = "amd-qdma",
1141 MODULE_DESCRIPTION("AMD QDMA driver");
H A Dqdma-comm-regs.c9 #include "qdma.h"
H A Dqdma.h24 #define QDMA_INTR_PREFIX "amd-qdma"
/linux/drivers/dma/
H A Dfsl-qdma.c141 * descriptor format with qDMA.
150 * by qDMA and dynamic debug field.
152 * @cmd: Command for QDMA (see FSL_QDMA_CMD_RWTTYPE and
175 /* qDMA status notification pre information */
187 struct fsl_qdma_engine *qdma; member
291 static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr) in qdma_readl() argument
293 return FSL_DMA_IN(qdma, addr, 32); in qdma_readl()
296 static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val, in qdma_writel() argument
299 FSL_DMA_OUT(qdma, addr, val, 32); in qdma_writel()
316 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma; in fsl_qdma_free_chan_resources()
[all …]
H A DMakefile41 obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
86 obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
H A DKconfig230 tristate "NXP Layerscape qDMA engine support"
237 Support the NXP Layerscape qDMA engine with command queue and legacy mode.
241 The qdma driver only work on SoCs with a DPAA hardware block.
773 source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.h246 /* QDMA TX Queue Configuration Registers */
250 /* QDMA Tx Queue Scheduler Configuration Registers */
264 /* QDMA TX Scheduler Rate Control Register */
267 /* QDMA Global Configuration Register */
279 /* QDMA V2 Global Configuration Register */
287 /* QDMA Flow Control Register */
292 /* QDMA Interrupt Status Register */
310 /* QDMA Interrupt grouping registers */
313 /* QDMA TX NUM */
319 /* QDMA V2 descriptor txd6 */
[all …]
H A Dmtk_eth_soc.c61 .qdma = {
127 .qdma = {
178 .qdma = {
807 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); in mtk_set_queue_speed()
1299 /* the qdma core needs scratch memory to be setup */
1353 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); in mtk_init_fq_dma()
1354 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); in mtk_init_fq_dma()
1355 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); in mtk_init_fq_dma()
1356 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); in mtk_init_fq_dma()
1683 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); in mtk_tx_map()
[all …]
/linux/drivers/dma/fsl-dpaa2-qdma/
H A DMakefile2 # Makefile for the NXP DPAA2 qDMA controllers
3 obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma.o dpdmai.o
H A DKconfig2 tristate "NXP DPAA2 QDMA"
8 NXP Data Path Acceleration Architecture 2 QDMA driver,
H A Ddpaa2-qdma.h71 struct dpaa2_qdma_engine *qdma; member
77 /* spinlock used by dpaa2 qdma driver */
H A Ddpdmai.c365 MODULE_DESCRIPTION("NXP DPAA2 QDMA driver");
/linux/Documentation/devicetree/bindings/pci/
H A Dxlnx,xdma-host.yaml19 - xlnx,qdma-host-3.00
24 - description: QDMA bridge register.
95 - xlnx,qdma-host-3.00
/linux/drivers/pci/controller/
H A Dpcie-xilinx-dma-pl.c82 QDMA, enumerator
135 if (port->variant->version == QDMA) in pcie_read()
143 if (port->variant->version == QDMA) in pcie_write()
200 if (port->variant->version == QDMA) in xilinx_pl_dma_pcie_map_bus()
747 if (port->variant->version == QDMA) { in xilinx_pl_dma_pcie_parse_dt()
823 .version = QDMA,
832 .compatible = "xlnx,qdma-host-3.00",
/linux/include/linux/platform_data/
H A Damd_qdma.h25 * struct qdma_platdata - Platform specific data for QDMA engine
H A Dedma.h33 * DaVinci hardware also has a "QDMA" mechanism which is not currently
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi816 qdma: dma-controller@8380000 { label
817 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
826 interrupt-names = "qdma-error", "qdma-queue0",
827 "qdma-queue1", "qdma-queue2", "qdma-queue3";
/linux/drivers/net/ethernet/sfc/
H A Def100_ethtool.c20 /* This is the maximum number of descriptor rings supported by the QDMA */
/linux/include/uapi/linux/
H A Dhdreg.h335 #define HDIO_GET_QDMA 0x0305 /* get use-qdma flag */
374 #define HDIO_SET_QDMA 0x032e /* change use-qdma flag */
/linux/drivers/usb/mtu3/
H A Dmtu3_qmu.c262 dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n", in mtu3_prepare_tx_gpd()
305 dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n", in mtu3_prepare_rx_gpd()
/linux/arch/arm64/boot/dts/airoha/
H A Den7581.dtsi365 reset-names = "fe", "pdma", "qdma",

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