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/freebsd/sys/contrib/device-tree/src/riscv/spacemit/
H A Dk1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/spacemit,k1-syscon.h>
8 /dts-v1/;
10 #address-cells = <2>;
11 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <24000000>;
20 cpu-map {
57 riscv,isa-base = "rv64i";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dnpcm750-pwm-fan.txt1 Nuvoton NPCM PWM and Fan Tacho controller device
3 The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
4 controller outputs and 16 Fan tachometer controller inputs.
6 The Nuvoton BMC NPCM8XX supports 12 Pulse-width modulation (PWM)
7 controller outputs and 16 Fan tachometer controller input
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H A Daspeed-pwm-tacho.txt1 ASPEED AST2400/AST2500 PWM and Fan Tacho controller device driver
3 The ASPEED PWM controller can support upto 8 PWM outputs. The ASPEED Fan Tacho
4 controller can support upto 16 Fan tachometer inputs.
6 There can be upto 8 fans supported. Each fan can have one PWM output and
9 Required properties for pwm-tacho node:
10 - #addres
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H A Daspeed,g6-pwm-tach.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/aspeed,g6-pwm-tach.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ASPEED G6 PWM and Fan Tach controller
11 - Billy Tsai <billy_tsai@aspeedtech.com>
14 The ASPEED PWM controller can support up to 16 PWM outputs.
15 The ASPEED Fan Tacho controller can support up to 16 fan tach input.
22 - aspeed,ast2600-pwm-tach
33 "#pwm-cells":
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/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k0500.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
27 ref_100m: clock-ref-100m {
28 compatible = "fixed-clock";
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H A Dloongson-2k2000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
34 ref_100m: clock-ref-100m {
35 compatible = "fixed-clock";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dkontron,sl28cpld.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Kontron's sl28cpld board management controller
10 - Michael Walle <michael@walle.cc>
13 The board management controller may contain different IP blocks like
14 watchdog, fan monitoring, PWM controller, interrupt controller and a
15 GPIO controller.
26 "#address-cells":
29 "#size-cells":
[all …]
H A Dairoha,en7581-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/airoha,en7581-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha EN7581 GPIO System Controller
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Lorenzo Bianconi <lorenzo@kernel.org>
14 Airoha EN7581 SoC GPIO system controller which provided a register map
15 for controlling the GPIO, pins and PWM of the SoC.
20 - const: airoha,en7581-gpio-sysctl
[all …]
H A Datmel,hlcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel's HLCD Controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
12 - Claudiu Beznea <claudiu.beznea@tuxon.dev>
15 The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two
16 subdevices, a PWM chip and a Display Controller.
21 - atmel,at91sam9n12-hlcdc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dmediatek,mt2712-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek PWM Controller
10 - John Crispin <john@phrozen.org>
13 - $ref: pwm.yaml#
18 - enum:
19 - mediatek,mt2712-pwm
20 - mediatek,mt6795-pwm
[all …]
H A Dpwm-sprd.txt1 Spreadtrum PWM controller
3 Spreadtrum SoCs PWM controller provides 4 PWM channels.
6 - compatible : Should be "sprd,ums512-pwm".
7 - reg: Physical base address and length of the controller's registers.
8 - clocks: The phandle and specifier referencing the controller's clocks.
9 - clock-names: Should contain following entries:
10 "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
11 "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
12 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
16 - assigned-clocks: Reference to the PWM clock entries.
[all …]
H A Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
14 (controller specific)
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H A Dpwm-zx.txt1 ZTE ZX PWM controller
4 - compatible: Should be "zte,zx296718-pwm".
5 - reg: Physical base address and length of the controller's registers.
6 - clocks : The phandle and specifier referencing the controller's clocks.
7 - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The
10 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
15 pwm: pwm@1439000 {
16 compatible = "zte,zx296718-pwm";
20 clock-names = "pclk", "wclk";
21 #pwm-cells = <3>;
H A Dpwm-hibvt.txt1 Hisilicon PWM controller
4 -compatible: should contain one SoC specific compatible string
6 "hisilicon,hi3516cv300-pwm"
7 "hisilicon,hi3519v100-pwm"
8 "hisilicon,hi3559v100-shub-pwm"
9 "hisilicon,hi3559v100-pwm
10 - reg: physical base address and length of the controller's registers.
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - resets: phandle and reset specifier for the PWM controller reset.
13 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
[all …]
H A Dpwm-sifive.txt1 SiFive PWM controller
3 Unlike most other PWM controllers, the SiFive PWM controller currently only
4 supports one period for all channels in the PWM. All PWMs need to run at
7 PWM RTL that corresponds to the IP block version numbers can be found
10 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
13 - compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
14 Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
15 PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
16 SiFive PWM v0 IP block with no chip integration tweaks.
17 Please refer to sifive-blocks-ip-versioning.txt for details.
[all …]
H A Dmediatek,pwm-disp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DISP_PWM Controller
10 - Jitao Shi <jitao.shi@mediatek.com>
13 - $ref: pwm.yaml#
18 - enum:
19 - mediatek,mt2701-disp-pwm
20 - mediatek,mt6595-disp-pwm
[all …]
H A Dpwm-bcm2835.txt1 BCM2835 PWM controller (Raspberry Pi controller)
4 - compatible: should be "brcm,bcm2835-pwm"
5 - reg: physical base address and length of the controller's registers
6 - clocks: This clock defines the base clock frequency of the PWM hardware
7 system, the period and the duty_cycle of the PWM signal is a multiple of
9 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
14 pwm@2020c000 {
15 compatible = "brcm,bcm2835-pwm";
18 #pwm-cells = <3>;
23 clk_pwm: pwm {
[all …]
H A Dbrcm,bcm7038-pwm.txt1 Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller)
5 - compatible: must be "brcm,bcm7038-pwm"
6 - reg: physical base address and length for this controller
7 - #pwm-cells: should be 2. See pwm.yaml in this directory for a description
9 - clocks: a phandle to the reference clock for this block which is fed through
15 pwm: pwm@f0408000 {
16 compatible = "brcm,bcm7038-pwm";
18 #pwm-cells = <2>;
H A Datmel,hlcdc-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/atmel,hlcdc-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel's HLCDC's PWM controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
12 - Claudiu Beznea <claudiu.beznea@tuxon.dev>
15 The LCDC integrates a Pulse Width Modulation (PWM) Controller. This block
17 display's contrast by software. LCDC_PWM is an 8-bit PWM signal that can be
[all …]
H A Dbrcm,kona-pwm.txt1 Broadcom Kona PWM controller device tree bindings
3 This controller has 6 channels.
6 - compatible: should contain "brcm,kona-pwm"
7 - reg: physical base address and length of the controller's registers
8 - clocks: phandle + clock specifier pair for the external clock
9 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a
12 Refer to clocks/clock-bindings.txt for generic clock consumer properties.
16 pwm: pwm@3e01a000 {
17 compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
20 #pwm-cells = <3>;
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Damlogic-c3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/reset/amlogic,c3-reset.h>
10 #include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
12 #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
13 #include <dt-bindings/power/amlogic,c3-pwrc.h>
14 #include <dt-bindings/gpio/amlogic-c3-gpio.h>
[all …]
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr8a7779.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-mvebu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell EBU GPIO controller
10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 - Andrew Lunn <andrew@lunn.ch>
16 - enum:
17 - marvell,armada-8k-gpio
18 - marvell,orion-gpio
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 lsio_bus_clk: clock-lsio-bus {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <100000000>;
14 clock-output-names = "lsio_bus_clk";
18 compatible = "simple-bus";
[all …]

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