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/linux/drivers/clk/keystone/
H A Dgate.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Clock driver for Keystone 2 based devices
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
17 /* PSC register offsets */
25 /* PSC module states */
44 * struct clk_psc_data - PSC data
45 * @control_base: Base address for a PSC control
46 * @domain_base: Base address for a PSC domain
47 * @domain_id: PSC domain id number
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Kepler/Hawking SoC clock nodes
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
15 reg-names = "control";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
23 reg-names = "control", "multiplier", "post-divider";
[all …]
H A Dkeystone-k2l-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 lamarr SoC clock nodes
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
15 reg-names = "control";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
23 reg-names = "control", "multiplier", "post-divider";
[all …]
H A Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 clock tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
[all …]
H A Dkeystone-k2e-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
10 #clock-cells = <0>;
11 compatible = "ti,keystone,main-pll-clock";
14 reg-names = "control", "multiplier", "post-divider";
18 #clock-cells = <0>;
19 compatible = "ti,keystone,pll-clock";
21 clock-output-names = "papllclk";
23 reg-names = "control";
27 #clock-cells = <0>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 #include <dt-bindings/clock/mpc512x-clock.h>
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&ipic>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
[all …]
H A Ddigsy_mtc.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 &gpt0 { gpio-controller; fsl,has-wdt; };
13 &gpt1 { gpio-controller; };
16 model = "intercontrol,digsy-mtc";
17 compatible = "intercontrol,digsy-mtc";
28 psc@2000 { // PSC1
32 psc@2200 { // PSC2
36 psc@2400 { // PSC3
40 psc@2600 { // PSC4
41 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
[all …]
H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
[all …]
H A Dmpc5200b.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&mpc5200_pic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
26 d-cache-line-size = <32>;
27 i-cache-line-size = <32>;
28 d-cache-size = <0x4000>; // L1, 16K
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H A Dmpc5125twr.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
11 #include <dt-bindings/clock/mpc512x-clock.h>
13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&ipic>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
[all …]
H A Duc101.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2006-2007 Secret Lab Technologies Ltd.
12 &gpt0 { gpio-controller; };
13 &gpt1 { gpio-controller; };
14 &gpt2 { gpio-controller; };
15 &gpt3 { gpio-controller; };
16 &gpt4 { gpio-controller; };
17 &gpt5 { gpio-controller; };
18 &gpt6 { gpio-controller; };
19 &gpt7 { gpio-controller; };
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5121-psc.txt1 MPC5121 PSC Device Tree Bindings
3 PSC in UART mode
4 ----------------
6 For PSC in UART mode the needed PSC serial devices
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
[all …]
H A Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
38 end of the compatible field. ie. A PSC in i2s mode would specify
[all …]
/linux/drivers/clk/davinci/
H A Dpsc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Clock driver for TI Davinci PSC controllers
9 * Murali Karicheri <m-karicheri2@ti.com>
12 * And: arch/arm/mach-davinci/psc.c
16 #include <linux/clk-provider.h>
27 #include <linux/reset-controller.h>
31 #include "psc.h"
33 /* PSC register offsets */
42 /* PSC module states */
65 * struct davinci_lpsc_clk - LPSC clock structure
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dti,keystone,psc-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,keystone,psc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI Keystone PSC clock
10 - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 - Murali Karicheri <m-karicheri2@ti.com>
15 const: ti,keystone,psc-clock
19 - description: PSC control
20 - description: Domain
[all …]
/linux/drivers/spi/
H A Dspi-mpc52xx-psc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC52xx PSC in SPI mode driver.
26 #define MCLK 20000000 /* PSC port MClk in hz */
30 struct mpc52xx_psc __iomem *psc; member
44 /* set clock freq, clock ramp, bits per work
50 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; in mpc52xx_psc_spi_transfer_setup()
52 cs->speed_hz = (t && t->speed_hz) in mpc52xx_psc_spi_transfer_setup()
53 ? t->speed_hz : spi->max_speed_hz; in mpc52xx_psc_spi_transfer_setup()
54 cs->bits_per_word = (t && t->bits_per_word) in mpc52xx_psc_spi_transfer_setup()
55 ? t->bits_per_word : spi->bits_per_word; in mpc52xx_psc_spi_transfer_setup()
[all …]
/linux/arch/powerpc/platforms/512x/
H A Dmpc512x_shared.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/fsl-diu-fb.h>
36 out_be32(&reset_module_base->rpr, 0x52535445); in mpc512x_restart()
38 out_be32(&reset_module_base->rcr, 0x2); in mpc512x_restart()
47 u8 gamma[0x300]; /* 32-bit aligned! */
48 struct diu_ad ad0; /* 32-bit aligned! */
54 /* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
62 /* lookup and enable the DIU clock */ in mpc512x_set_pixel_clock()
63 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu"); in mpc512x_set_pixel_clock()
70 /* backwards compat with device trees that lack clock specs */ in mpc512x_set_pixel_clock()
[all …]
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * common clock driver support for the MPC512x platform
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
69 /* data required for the OF clock provider registration */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
90 * those differences can get folded into this clock provider support
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
[all …]
/linux/sound/soc/fsl/
H A Dmpc5200_psc_i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Freescale MPC5200 PSC in I2S mode
23 * This driver currently only supports the PSC running in I2S slave mode,
31 * PSC_I2S_FORMATS: audio formats supported by the PSC I2S mode
44 dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i" in psc_i2s_hw_params()
64 dev_dbg(psc_dma->dev, "invalid format\n"); in psc_i2s_hw_params()
65 return -EINVA in psc_i2s_hw_params()
[all...]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dsw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2013 Realtek Corporation.*/
25 * 0 - Disable ASPM, in rtl88e_init_aspm_vars()
26 * 1 - Enable ASPM without Clock Req, in rtl88e_init_aspm_vars()
27 * 2 - Enable ASPM with Clock Req, in rtl88e_init_aspm_vars()
28 * 3 - Alwyas Enable ASPM with Clock Req, in rtl88e_init_aspm_vars()
29 * 4 - Always Enable ASPM without Clock Req. in rtl88e_init_aspm_vars()
32 rtlpci->const_pci_aspm = 3; in rtl88e_init_aspm_vars()
34 /*Setting for PCI-E device */ in rtl88e_init_aspm_vars()
35 rtlpci->const_devicepci_aspm_setting = 0x03; in rtl88e_init_aspm_vars()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dsw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
29 * 0 - Disable ASPM, in rtl92c_init_aspm_vars()
30 * 1 - Enable ASPM without Clock Req, in rtl92c_init_aspm_vars()
31 * 2 - Enable ASPM with Clock Req, in rtl92c_init_aspm_vars()
32 * 3 - Alwyas Enable ASPM with Clock Req, in rtl92c_init_aspm_vars()
33 * 4 - Always Enable ASPM without Clock Req. in rtl92c_init_aspm_vars()
36 rtlpci->const_pci_aspm = 3; in rtl92c_init_aspm_vars()
38 /*Setting for PCI-E device */ in rtl92c_init_aspm_vars()
39 rtlpci->const_devicepci_aspm_setting = 0x03; in rtl92c_init_aspm_vars()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dsw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
29 * 0 - Disable ASPM, in rtl92ee_init_aspm_vars()
30 * 1 - Enable ASPM without Clock Req, in rtl92ee_init_aspm_vars()
31 * 2 - Enable ASPM with Clock Req, in rtl92ee_init_aspm_vars()
32 * 3 - Alwyas Enable ASPM with Clock Req, in rtl92ee_init_aspm_vars()
33 * 4 - Always Enable ASPM without Clock Req. in rtl92ee_init_aspm_vars()
36 rtlpci->const_pci_aspm = 3; in rtl92ee_init_aspm_vars()
38 /*Setting for PCI-E device */ in rtl92ee_init_aspm_vars()
39 rtlpci->const_devicepci_aspm_setting = 0x03; in rtl92ee_init_aspm_vars()
[all …]
/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_common.c25 { .compatible = "fsl,mpc5200-xlb", },
26 { .compatible = "mpc5200-xlb", },
30 { .compatible = "fsl,mpc5200-immr", },
31 { .compatible = "fsl,mpc5200b-immr", },
32 { .compatible = "simple-bus", },
71 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
72 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
77 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
81 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
110 { .compatible = "fsl,mpc5200-gpt", },
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dsw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
25 * 0 - Disable ASPM, in rtl92s_init_aspm_vars()
26 * 1 - Enable ASPM without Clock Req, in rtl92s_init_aspm_vars()
27 * 2 - Enable ASPM with Clock Req, in rtl92s_init_aspm_vars()
28 * 3 - Alwyas Enable ASPM with Clock Req, in rtl92s_init_aspm_vars()
29 * 4 - Always Enable ASPM without Clock Req. in rtl92s_init_aspm_vars()
32 rtlpci->const_pci_aspm = 2; in rtl92s_init_aspm_vars()
34 /*Setting for PCI-E device */ in rtl92s_init_aspm_vars()
35 rtlpci->const_devicepci_aspm_setting = 0x03; in rtl92s_init_aspm_vars()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dsw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
30 * 0 - Disable ASPM, in rtl92d_init_aspm_vars()
31 * 1 - Enable ASPM without Clock Req, in rtl92d_init_aspm_vars()
32 * 2 - Enable ASPM with Clock Req, in rtl92d_init_aspm_vars()
33 * 3 - Alwyas Enable ASPM with Clock Req, in rtl92d_init_aspm_vars()
34 * 4 - Always Enable ASPM without Clock Req. in rtl92d_init_aspm_vars()
37 rtlpci->const_pci_aspm = 3; in rtl92d_init_aspm_vars()
39 /*Setting for PCI-E device */ in rtl92d_init_aspm_vars()
40 rtlpci->const_devicepci_aspm_setting = 0x03; in rtl92d_init_aspm_vars()
[all …]

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