| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4.c | 255 …ay_cfg *svp_expanded_display_cfg, struct dml2_display_cfg_programming *programming, struct dml2_co… in pack_mode_programming_params_with_implicit_subvp() argument
266 …memcpy(&programming->display_config, &display_cfg->display_config, sizeof(struct dml2_display_cfg)… in pack_mode_programming_params_with_implicit_subvp()
269 …arb_params(&display_cfg->display_config, &core->clean_me_up.mode_lib, &programming->global_regs.ar… in pack_mode_programming_params_with_implicit_subvp()
272 …watermarks(&display_cfg->display_config, &core->clean_me_up.mode_lib, &programming->global_regs.wm… in pack_mode_programming_params_with_implicit_subvp()
276 programming->fams2_required = display_cfg->stage3.fams2_required; in pack_mode_programming_params_with_implicit_subvp()
278 …et_global_fams2_programming(&core->clean_me_up.mode_lib, display_cfg, &programming->fams2_global_c… in pack_mode_programming_params_with_implicit_subvp()
282 for (stream_index = 0; stream_index < programming->display_config.num_streams; stream_index++) { in pack_mode_programming_params_with_implicit_subvp()
287 …programming->stream_programming[stream_index].stream_descriptor = &programming->display_config.str… in pack_mode_programming_params_with_implicit_subvp()
290 …programming->stream_programming[stream_index].num_odms_required = display_cfg->mode_support_result… in pack_mode_programming_params_with_implicit_subvp()
295 programming->stream_programming[stream_index].phantom_stream.enabled = true; in pack_mode_programming_params_with_implicit_subvp()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/ |
| H A D | dml2_dpmm_dcn4.c | 85 …in_out->programming->min_clocks.dcn4x.active.uclk_khz = dml_round_up(min_uclk_bw > min_uclk_latenc… in calculate_system_active_minimums()
86 …in_out->programming->min_clocks.dcn4x.active.fclk_khz = dml_round_up(min_fclk_bw > min_fclk_latenc… in calculate_system_active_minimums()
87 …in_out->programming->min_clocks.dcn4x.active.dcfclk_khz = dml_round_up(min_dcfclk_bw > min_dcfclk_… in calculate_system_active_minimums()
126 …in_out->programming->min_clocks.dcn4x.svp_prefetch.uclk_khz = dml_round_up(min_uclk_bw > min_uclk_… in calculate_svp_prefetch_minimums()
127 …in_out->programming->min_clocks.dcn4x.svp_prefetch.fclk_khz = dml_round_up(min_fclk_bw > min_fclk_… in calculate_svp_prefetch_minimums()
128 …in_out->programming->min_clocks.dcn4x.svp_prefetch.dcfclk_khz = dml_round_up(min_dcfclk_bw > min_d… in calculate_svp_prefetch_minimums()
157 …in_out->programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz = dml_round_up(min_uclk_bw… in calculate_svp_prefetch_minimums()
158 …in_out->programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz = dml_round_up(min_fclk_bw… in calculate_svp_prefetch_minimums()
159 …in_out->programming->min_clocks.dcn4x.svp_prefetch_no_throttle.dcfclk_khz = dml_round_up(min_dcfcl… in calculate_svp_prefetch_minimums()
181 …in_out->programming->min_clocks.dcn4x.idle.uclk_khz = dml_round_up(min_uclk_avg > min_uclk_latency… in calculate_idle_minimums()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/ |
| H A D | dml_top.c | 99 …ruct dml2_display_cfg_programming *dpmm_programming = &dml->dpmm_instance.dpmm_scratch.programming; in dml2_check_mode_supported()
134 l->dppm_map_mode_params.programming = dpmm_programming; in dml2_check_mode_supported()
159 memset(in_out->programming, 0, sizeof(struct dml2_display_cfg_programming)); in dml2_build_mode_programming()
161 …memcpy(&in_out->programming->display_config, in_out->display_config, sizeof(struct dml2_display_cf… in dml2_build_mode_programming()
186 l->informative_params.programming = in_out->programming; in dml2_build_mode_programming()
225 l->informative_params.programming = in_out->programming; in dml2_build_mode_programming()
230 in_out->programming->informative.failed_mcache_validation = true; in dml2_build_mode_programming()
303 * Populate mcache programming in dml2_build_mode_programming()
306 …in_out->programming->plane_programming[i].mcache_allocation = l->base_display_config_with_meta.sta… in dml2_build_mode_programming()
315 l->dppm_map_mode_params.programming = in_out->programming; in dml2_build_mode_programming()
[all …]
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| H A D | dml2_top_soc15.c | 322 * Takes an input set of mcache boundaries and finds the appropriate setting of cache programming.
323 * Returns true if a valid set of programming can be made, and false otherwise. "Valid" means
779 …ruct dml2_display_cfg_programming *dpmm_programming = &dml->dpmm_instance.dpmm_scratch.programming; in dml2_top_soc15_check_mode_supported()
812 l->dppm_map_mode_params.programming = dpmm_programming; in dml2_top_soc15_check_mode_supported()
837 memset(in_out->programming, 0, sizeof(struct dml2_display_cfg_programming)); in dml2_top_soc15_build_mode_programming()
839 …memcpy(&in_out->programming->display_config, in_out->display_config, sizeof(struct dml2_display_cf… in dml2_top_soc15_build_mode_programming()
863 l->informative_params.programming = in_out->programming; in dml2_top_soc15_build_mode_programming()
902 l->informative_params.programming = in_out->programming; in dml2_top_soc15_build_mode_programming()
907 in_out->programming->informative.failed_mcache_validation = true; in dml2_top_soc15_build_mode_programming()
980 * Populate mcache programming in dml2_top_soc15_build_mode_programming()
[all …]
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-fpga-manager | 13 wrong during FPGA programming (something that the driver can't
30 * write init = preparing FPGA for programming
31 * write init error = Error while preparing FPGA for programming
33 * write error = Error while programming
34 * write complete = Doing post programming steps
35 * write complete error = Error while doing post programming
43 If FPGA programming operation fails, it could be caused by crc
46 programming errors to userspace. This is a list of strings for
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| H A D | dml21_wrapper.c | 30 …(*dml_ctx)->v21.mode_programming.programming = kzalloc(sizeof(struct dml2_display_cfg_programming)… in dml21_allocate_memory()
31 if (!((*dml_ctx)->v21.mode_programming.programming)) in dml21_allocate_memory()
115 kfree(dml2->v21.mode_programming.programming); in dml21_destroy()
131 …memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.ar… in dml21_calculate_rq_and_dlg_params()
134 …context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_reg… in dml21_calculate_rq_and_dlg_params()
141 pln_prog = &in_ctx->v21.mode_programming.programming->plane_programming[dml_prog_idx]; in dml21_calculate_rq_and_dlg_params()
146 …stream_prog = &in_ctx->v21.mode_programming.programming->stream_programming[pln_prog->plane_descri… in dml21_calculate_rq_and_dlg_params()
260 …_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.progr… in dml21_check_mode_support()
299 dml_phantom_prog_idx = dml_ctx->v21.mode_programming.programming->display_config.num_planes; in dml21_prepare_mcache_programming()
301 /* Build mcache programming parameters per plane per pipe */ in dml21_prepare_mcache_programming()
[all …]
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| H A D | dml21_utils.c | 65 …if (dml_ctx->v21.mode_programming.programming->plane_programming[i].plane_descriptor->stream_index… in find_valid_pipe_idx_for_stream_index()
105 …dml_stream_index = dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_idx].pla… in dml21_find_dc_pipes_for_plane()
331 …for (dml_stream_index = 0; dml_stream_index < dml_ctx->v21.mode_programming.programming->display_c… in dml21_handle_phantom_streams_planes()
333 …if (dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_index].phantom_stream… in dml21_handle_phantom_streams_planes()
348 &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_index]); in dml21_handle_phantom_streams_planes()
354 …for (dml_plane_index = 0; dml_plane_index < dml_ctx->v21.mode_programming.programming->display_con… in dml21_handle_phantom_streams_planes()
355 …if (dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_index].plane_descriptor… in dml21_handle_phantom_streams_planes()
366 &dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_index]); in dml21_handle_phantom_streams_planes()
390 if (dml_ctx->v21.mode_programming.programming->fams2_required) { in dml21_build_fams2_programming()
416 … &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_base_params, in dml21_build_fams2_programming()
[all …]
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| H A D | dml21_translation_helper.c | 726 // Placeholder for programming the array_mode in populate_dml21_surface_config_from_plane_state()
1075 …context->bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1076 …context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x… in dml21_copy_clocks_to_dc_state()
1077 …context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1078 …context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.a… in dml21_copy_clocks_to_dc_state()
1079 …context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks… in dml21_copy_clocks_to_dc_state()
1080 …context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dc… in dml21_copy_clocks_to_dc_state()
1081 …context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = in_ctx->v21.mode_programming.programming->min_c… in dml21_copy_clocks_to_dc_state()
1082 …context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming-… in dml21_copy_clocks_to_dc_state()
1083 …context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk… in dml21_copy_clocks_to_dc_state()
[all …]
|
| /linux/Documentation/driver-api/fpga/ |
| H A D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
7 The in-kernel API for FPGA programming is a combination of APIs from
9 trigger FPGA programming is fpga_region_program_fpga().
31 bridges to control during programming or it has a pointer to a function that
71 /* Add info to region and do the programming */
84 API for programming an FPGA
|
| H A D | intro.rst | 26 If you are adding a new FPGA or a new method of programming an FPGA,
36 region of an FPGA during programming. They are disabled before
37 programming begins and re-enabled afterwards. An FPGA bridge may be
|
| /linux/tools/memory-model/Documentation/ |
| H A D | references.txt | 34 Proceedings of the 32Nd ACM SIGPLAN Conference on Programming
41 ACM SIGPLAN Conference on Programming Language Design and
56 SIGPLAN-SIGACT Symposium on Principles of Programming Languages
63 Principles of Programming Languages (POPL 2017). ACM, New York,
69 Proceedings of the ACM on Programming Languages, Volume 2, Issue
92 Programming Languages and Operating Systems (ASPLOS 2018). ACM,
|
| /linux/drivers/net/wireless/rsi/ |
| H A D | rsi_boot_params.h | 58 /* structure to store configs related to TAPLL programming */
64 /* structure to store configs related to PLL960 programming */
71 /* structure to store configs related to AFEPLL programming */
92 /* structure to store configs related to UMAC clk programming */
149 /* WDT programming values */
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| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_txrx_common.h | 87 * i40e_rx_is_programming_status - check for programming status descriptor
91 * is a programming status descriptor for flow director or FCoE
97 /* The Rx filter programming status and SPH bit occupy the same in i40e_rx_is_programming_status()
100 * programming status descriptor. in i40e_rx_is_programming_status()
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| /linux/Documentation/driver-api/soundwire/ |
| H A D | error_handling.rst | 16 Improvements could be invalidating an entire programming sequence and
22 that bus clashes due to programming errors (two streams using the same bit
34 be applied. In case of a bad programming (command sent to non-existent
38 backtracking and restarting the entire programming sequence might be a
|
| /linux/Documentation/misc-devices/ |
| H A D | c2port.rst | 26 C2 Interface used for in-system programming of micro controllers.
38 - AN127: FLASH Programming via the C2 Interface at
45 banging) designed to enable in-system programming, debugging, and
47 this code supports only flash programming but extensions are easy to
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| H A D | dml_top.h | 31 * Determines the full (optimized) programming for the input mode. Returns minimum
32 * clocks as well as dchub register programming values for all pipes, additional meta
38 * Determines the correct per pipe mcache register programming for a valid mode.
|
| /linux/drivers/misc/c2port/ |
| H A D | core.c | 497 /* Target the C2 flash programming control register for C2 data in __c2port_store_flash_access()
501 /* Write the first keycode to enable C2 Flash programming */ in __c2port_store_flash_access()
506 /* Write the second keycode to enable C2 Flash programming */ in __c2port_store_flash_access()
512 * C2 flash programming */ in __c2port_store_flash_access()
535 dev_err(c2dev->dev, "cannot enable %s flash programming\n", in c2port_store_flash_access()
550 /* Target the C2 flash programming data register for C2 data register in __c2port_write_flash_erase()
570 /* Read flash programming interface status */ in __c2port_write_flash_erase()
644 /* Target the C2 flash programming data register for C2 data register in __c2port_read_flash_data()
663 /* Read flash programming interface status */ in __c2port_read_flash_data()
695 /* Read flash programming interfac in __c2port_read_flash_data()
[all...] |
| /linux/include/soc/at91/ |
| H A D | sama7-ddr.h | 73 #define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */
74 #define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset …
76 #define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */
77 #define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | display_mode_core_structs.h | 656 …/ <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
663 /// @brief To control the clk usage for model programming
685 struct dml_hw_resource_st hw; //< brief for mode programming
686 struct dml_clk_cfg_st clk_overrides; //< brief for mode programming clk override
689 /// @brief DML mode evaluation and programming policy
690 /// Those knobs that affect mode support and mode programming
703 … support the given display configuration. User can tell use the output DCFCLK for mode programming.
725 …t immediate flip at the max combine setting; determine in mode support and used in mode programming
792 …/ <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage
821 // Physical info; only using for programming
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/ |
| H A D | dml2_internal_shared_types.h | 90 struct dml2_display_cfg_programming *programming; member
103 struct dml2_display_cfg_programming *programming; member
107 struct dml2_display_cfg_programming programming; member
399 * Outputs (also Input the clk freq are also from programming struct)
401 struct dml2_display_cfg_programming *programming; member
411 // If this is set, then the mode was supported, and mode programming
413 // Otherwise, mode programming was not run, because mode support failed.
419 struct dml2_display_cfg_programming *programming; member
|
| /linux/drivers/ata/ |
| H A D | pata_optidma.c | 164 /* Commence primary programming sequence */ in optidma_mode_setup()
178 /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */ in optidma_mode_setup()
184 /* Note: at this point our programming is incomplete. We are in optidma_mode_setup()
235 * DMA programming. The architecture of the Firestar makes it easier
250 * DMA programming. The architecture of the Firestar makes it easier
265 * DMA programming. The architecture of the Firestar makes it easier
280 * DMA programming. The architecture of the Firestar makes it easier
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| /linux/drivers/fpga/tests/ |
| H A D | fpga-region-test.c | 62 * of programming cycles. The internals of the programming sequence are
114 * FPGA Region programming test. The Region must call get_bridges() to get
115 * and control the bridges, and then the Manager for the actual programming.
|
| /linux/Documentation/process/ |
| H A D | programming-language.rst | 3 Programming Language
6 The kernel is written in the C programming language [c-language]_.
37 The kernel has experimental support for the Rust programming language
|
| /linux/Documentation/input/ |
| H A D | input_kapi.rst | 12 input-programming
13 gameport-programming
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | calxeda-combophy.yaml | 14 Programming the PHYs is typically handled by those device drivers,
31 description: device ID for programming the ComboPHY.
|