programmable\-clocks (full) in projects: freebsd

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Searched +full:programmable +full:- +full:clocks (Results 1 – 19 of 19) sorted by relevance

/illumos-gate/usr/src/data/perfmon/NHM-EP/
H A D	NehalemEP_core_V2.json	635 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 636 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 669 "BriefDescription": "Cycles when thread is not halted (programmable counter)", 670 "PublicDescription": "Cycles when thread is not halted (programmable counter)", 1009 "BriefDescription": "Computational floating-point operations executed", 1010 "PublicDescription": "Computational floating-point operations executed", 1230 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", 1231 "PublicDescription": "Instructions retired (Programmable counter and Precise Event)", 1281 "BriefDescription": "Retired floating-point operations (Precise Event)", 1282 "PublicDescription": "Retired floating-point operations (Precise Event)", [all …]
/illumos-gate/usr/src/data/perfmon/NHM-EX/
H A D	NehalemEX_core_V2.json	635 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 636 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 669 "BriefDescription": "Cycles when thread is not halted (programmable counter)", 670 "PublicDescription": "Cycles when thread is not halted (programmable counter)", 1009 "BriefDescription": "Computational floating-point operations executed", 1010 "PublicDescription": "Computational floating-point operations executed", 1230 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", 1231 "PublicDescription": "Instructions retired (Programmable counter and Precise Event)", 1281 "BriefDescription": "Retired floating-point operations (Precise Event)", 1282 "PublicDescription": "Retired floating-point operations (Precise Event)", [all …]
/illumos-gate/usr/src/data/perfmon/WSM-EP-DP/
H A D	WestmereEP-DP_core_V2.json	669 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 670 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 703 "BriefDescription": "Cycles when thread is not halted (programmable counter)", 704 "PublicDescription": "Cycles when thread is not halted (programmable counter)", 1145 "BriefDescription": "Computational floating-point operations executed", 1146 "PublicDescription": "Computational floating-point operations executed", 1366 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", 1367 "PublicDescription": "Instructions retired (Programmable counter and Precise Event)", 1417 "BriefDescription": "Retired floating-point operations (Precise Event)", 1418 "PublicDescription": "Retired floating-point operations (Precise Event)", [all …]
/illumos-gate/usr/src/data/perfmon/WSM-EP-SP/
H A D	WestmereEP-SP_core_V2.json	669 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 670 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 703 "BriefDescription": "Cycles when thread is not halted (programmable counter)", 704 "PublicDescription": "Cycles when thread is not halted (programmable counter)", 1111 "BriefDescription": "Computational floating-point operations executed", 1112 "PublicDescription": "Computational floating-point operations executed", 1332 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", 1333 "PublicDescription": "Instructions retired (Programmable counter and Precise Event)", 1383 "BriefDescription": "Retired floating-point operations (Precise Event)", 1384 "PublicDescription": "Retired floating-point operations (Precise Event)", [all …]
/illumos-gate/usr/src/data/perfmon/WSM-EX/
H A D	WestmereEX_core_V2.json	669 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 670 …ription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", 703 "BriefDescription": "Cycles when thread is not halted (programmable counter)", 704 "PublicDescription": "Cycles when thread is not halted (programmable counter)", 1145 "BriefDescription": "Computational floating-point operations executed", 1146 "PublicDescription": "Computational floating-point operations executed", 1366 "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", 1367 "PublicDescription": "Instructions retired (Programmable counter and Precise Event)", 1417 "BriefDescription": "Retired floating-point operations (Precise Event)", 1418 "PublicDescription": "Retired floating-point operations (Precise Event)", [all …]
/illumos-gate/usr/src/lib/libjedec/common/
H A D	spd_ddr3.h	21 * based on JEDEC Standard 21-C Section Annex K: Serial Presence Detect 26 * o Base Configuration and DRAM parameters (bytes 0x00-0x3b) 27 * o Standard Module Parameters (bytes 0x40-0x74) these vary on whether 29 * o Manufacturing Information (bytes 0x75-0xaf) 30 * o End User Programmable data (0xb0-0xff). 74 * is, which tells us what the module-specific section contents are. These bits, 335 * UDIMM: Raw Card Extension, Module Nominal Height. Bits 7-5 here have a raw 356 * bit for bits 4-0. We do not define each meaning of these bit combinations in 430 * RDIMM: SSTE32882: RC3 / RC2 - Drive Strength, Command/Address. The lower 442 * RDIMM: SSTE32882: RC5 / RC4 - Drive Strength, Control and Clock [all …]
/illumos-gate/usr/src/uts/sun/io/eri/
H A D	eri_mac.h	40 /* The Descriptor Ring base Addresses must be 2K-byte aligned / 45 The transmit and receiver Descriptor Rings are organized as "wrap-around 46 * descriptors and are of programmable size. 47 * Each descriptor consists of two double-word entries: a control/status entry 49 * The no. of entries is programmable in binary increments, from 32 to 8192. 58 * ----------------------------- 60 * ----------------------------- 70 #define ERI_TMD_BUFSIZE (0x7fff << 0) /* 0-14 : Tx Data buffer size / 71 / valid values in range 0 - 17k / 72 #define ERI_TMD_CSSTART (0x3f << 15) / 15-20 : Checksum start offset */ [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/documentation/
H A D	ecore.tex	1 %---------------------------------------------------------------------------------------- 3 %---------------------------------------------------------------------------------------- 5 \documentclass[11pt,fleqn,hidelinks,oneside]{book} % Default font size and left-justified equations 8 %---------------------------------------------------------------------------------------- 40 %---------------------------------------------------------------------------------------- 44 %\lstset{belowskip=-20pt plus 2pt} 56 \newcommand{\mlisti}[2]{\item {\textcolor{red}{#1} -- #2}} 66 \advance\hsize by -2\columnsep% 90 \newcommand{\greycom}[2]{\greybox{\textcolor{red}{#1} -- #2}} 131 \includegraphics[width=0.5\textwidth]{./qlogic-logo}~\\[3cm] [all …]
/illumos-gate/usr/src/data/perfmon/SKX/
H A D	skylakex_uncore_v1.24.json	857 …s from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory stat… 946 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", 947 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s… 964 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", 965 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st… 982 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ… 983 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss… 1000 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ… 1001 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory wri… 1019 …"PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory c… [all …]
/illumos-gate/usr/src/data/perfmon/CLX/
H A D	cascadelakex_uncore_v1.11.json	857 …s from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory stat… 946 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", 947 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s… 964 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", 965 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st… 982 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ… 983 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss… 1000 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ… 1001 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory wri… 1019 …"PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory c… [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… 149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D	57712_reg.h	3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32 9 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 14 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 15 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 16 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 17 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… [all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A D	hxge_peu_hw.h	230 * Master Data Parity Error - set if all the following conditions 234 * Fast Back-to-Back Capable (N/A in PCIE) 236 * Capabilities List - presence of extended capability item. 239 * Fast Back-to-Back Enable (N/A in PCIE) 244 * The device can issue Memory Write-and-Invalidate commands (N/A 346 * Multi-Function Device: dbi writeable 374 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0 432 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX 489 * Description: Virtualization BAR0 - Previously for Hydra 566 * Subsystem ID as assigned by PCI-SIG : dbi writeable [all …]
/illumos-gate/usr/src/data/perfmon/BDX/
H A D	broadwellx_uncore_v17.json	20 "BriefDescription": "Uncore Clocks", 34 …ed in Counter 0. The filtering available is found in the control register - threshold, invert an… 60 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer… 73 …- this includes code, data, prefetches and hints coming from L2. This has numerous filters availa… 86 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer… 99 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer… 112 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer… 125 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer… 280 "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0", 294 …X -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP directio… [all …]
/illumos-gate/usr/src/uts/common/io/sfxge/common/
H A D	efx_regs_mcdi.h	2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 33 /* Power-on reset state / 55 / The 'doorbell' addresses are hard-wired to alert the MC when written / 58 / The rest of these are firmware-defined / 66 / Values to be written to the per-port status dword in shared 95 * \| \| \--- Response 96 * \| \------- Error 97 * \------------------------------ Resync (always set) 152 * - To complete a shared memory request if XFLAGS_EVREQ was set 153 * - As a notification (link state, i2c event), controlled [all …]