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/freebsd/sys/contrib/device-tree/Bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dux500.txt1 Clock bindings for ST-Ericsson Ux500 clocks
4 - compatible : shall contain only one of the following:
5 "stericsson,u8500-clks"
6 "stericsson,u8540-clks"
7 "stericsson,u9540-clks"
8 - reg : shall contain base register location and length for
13 - prcmu-clock: a subnode with one clock cell for PRCMU (power,
14 reset, control unit) clocks. The cell indicates which PRCMU
15 clock in the prcmu-clock node the consumer wants to use.
16 - prcc-periph-clock: a subnode with two clock cells for
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H A Dsilabs,si5341.txt1 Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
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H A Didt,versaclock5.txt1 Binding for IDT VersaClock 5,6 programmable i2c clock generators.
3 The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
4 generators providing from 3 to 12 output clocks.
9 - compatible: shall be one of
16 - reg: i2c device address, shall be 0x68 or 0x6a.
17 - #clock-cells: from common clock binding; shall be set to 1.
18 - clocks: from common clock binding; list of parent clock handles,
19 - 5p49v5923 and
23 - 5p49v5933 and
24 - 5p49v5935: (optional) property not present (internal
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H A Dsilabs,si5351.txt1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
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H A Didt,versaclock5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: IDT VersaClock 5 and 6 programmable I2C clock generators
10 The IDT VersaClock 5 and VersaClock 6 are programmable I2C
11 clock generators providing from 3 to 12 output clocks.
16 - 5P49V5923:
17 0 -- OUT0_SEL_I2CB
18 1 -- OUT1
19 2 -- OUT2
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H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schema
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H A Dmaxim,max9485.txt1 Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
3 This device exposes 4 clocks in total:
5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
6 - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
14 - compatible: "maxim,max9485"
15 - clocks: Input clock, must provide 27.000 MHz
16 - clock-name
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H A Dti,cdce706.txt1 Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
7 - compatible: shall be "ti,cdce706".
8 - reg: i2c device address, shall be in range [0x68...0x6b].
9 - #clock-cells: from common clock binding; shall be set to 1.
10 - clocks: from common clock binding; list of parent clock
13 - clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0
16 single-ended LVCMOS inputs configuration.
20 clocks {
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
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H A Dapple,nco.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Povišer <povik+lin@cutebit.org>
14 such as the t8103 (M1) is a programmable clock generator performing
23 - enum:
24 - apple,t6000-nco
25 - apple,t8103-nco
26 - apple,t8112-nco
27 - const: apple,nco
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
12 by a programmable prescaler, break input feature, PWM outputs and
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
15 driven by a programmable prescaler and PWM outputs.
16 - basic timers consist of a 16-bit auto-reload counter driven by a
17 programmable prescaler.
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Daspeed,ast2600-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Billy Tsai <billy_tsai@aspeedtech.com>
13 • 10-bits resolution for 16 voltage channels.
16 • Channel scanning can be non-continuous.
17 • Programmable ADC clock frequency.
18 • Programmable upper and lower threshold for each channels.
21 • Built-in a compensating method.
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/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
22 The programmable nature of the PRUs provide flexibility to implement custom
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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,coresight-dynamic-funnel.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Programmable Trace Bus Funnel
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
23 The Coresight funnel merges 2-8 trace sources into a single trace
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H A Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-ct
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H A Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
26 programmable channels, usually 4, but again implementation defined and
29 programmable.
38 indicate this feature (arm,coresight-cti-v8-arch).
53 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
60 Note that some hardware trigger signals can be connected to non-CoreSight
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qo
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dnxp,sysctr-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bai Ping <ping.bai@nxp.com>
13 The system counter(sys_ctr) is a programmable system counter
16 is always powered and support multiple, unrelated clocks. The
22 - nxp,imx95-sysctr-timer
23 - nxp,sysctr-timer
31 clocks:
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H A Drenesas,tpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yoshinori Sato <ysato@users.sourceforge.jp>
14 programmable compare match.
22 '#pwm-cells': false
24 - compatible
32 - description: First channel
33 - description: Second channel
35 clocks:
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H A Drenesas,tpu.txt4 programmable compare match.
9 - compatible: must contain "renesas,tpu"
10 - reg: base address and length of the registers block in 2 channel.
11 - clocks: a list of phandle, one for each entry in clock-names.
12 - clock-names: must contain "peripheral_clk" for the functional clock.
19 clocks = <&pclk>;
20 clock-names = "peripheral_clk";
/freebsd/lib/libpmc/
H A Dpmc.sandybridgeuc.345 .Bl -tag -width "Li PMC_CLASS_UCP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
61 .%N "Order Number: 253669-039US"
68 Not all CPUs in this family implement fixed-function counters.
69 .Ss SANDYBRIDGE UNCORE PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
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H A Dpmc.haswelluc.345 .Bl -tag -width "Li PMC_CLASS_UCP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
61 .%N "Order Number: 325462-045US"
68 Not all CPUs in this family implement fixed-function counters.
69 .Ss HASWELL UNCORE PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
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/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dopencores,pwm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Qiu <william.qiu@starfivetech.com>
14 mode, the PTC core generates binary signal with user-programmable low and
15 high periods. All PTC counters and registers are 32-bit.
18 - $ref: pwm.yaml#
23 - enum:
24 - starfive,jh7100-pwm
25 - starfive,jh7110-pwm
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/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Ddigicolor-wdt.txt4 "Agent Communication" block. This block includes the eight programmable system
10 - compatible : Should be "cnxt,cx92755-wdt"
11 - reg : Specifies base physical address and size of the registers
12 - clocks : phandle; specifies the clock that drives the timer
16 - timeout-sec : Contains the watchdog timeout in seconds
21 compatible = "cnxt,cx92755-wdt";
23 clocks = <&main_clk>;
24 timeout-sec = <15>;

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