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/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dlattice,sysconfig.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
23 - lattice,sysconfig-ecp5
28 program-gpios:
34 init-gpios:
40 done-gpios:
47 - compatible
48 - reg
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx53-ard.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "fsl,imx53-ard", "fsl,imx53";
20 eim-cs1@f4000000 {
21 #address-cell
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H A Dimx6qdl-sabreauto.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
11 stdout-path = &uart4;
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_gpio_leds>;
24 led-user {
26 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
30 gpio-keys {
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H A Dimx6q-display5.dtsi5 * This file is dual-licensed: you can use it either under the terms
11 * License version 2. This program is licensed "as is" without
38 /dts-v1/;
42 #include <dt-bindings/gpio/gpio.h>
43 #include <dt-bindings/pwm/pwm.h>
44 #include <dt-bindings/sound/fsl-imx-audmux.h>
56 compatible = "pwm-backlight";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_backlight>;
60 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio.txt4 1) gpios property
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
9 for compatibility reasons (resolving to the "gpios" property), it is not allowed
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
15 cases should they contain more than one. If your device uses several GPIOs with
17 meaningful name. The only case where an array of GPIOs is accepted is when
18 several GPIOs serve the same function (e.g. a parallel data line).
20 The exact purpose of each gpios property must be documented in the device tree
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H A Dspear_spics.txt10 Chipselects can be controlled by software by turning them as GPIOs. SPEAr
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsmsc911x.txt1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115"
5 - reg : Address and length of the io space for SMSC LAN
6 - interrupts : one or two interrupt specifiers
7 - The first interrupt is the SMSC LAN interrupt line
8 - The second interrupt (if present) is the PME (power
11 - phy-mode : See ethernet.txt file in the same directory
14 - reg-shift : Specify the quantity to shift the register offsets by
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high
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H A Dsmsc,lan9115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: ethernet-controller.yaml#
18 - const: smsc,lan9115
19 - items:
20 - enum:
21 - smsc,lan89218
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
29 program; should be used in cases where the MAC address assigned
30 to the device by the boot program is different from the
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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dmarvell.txt2 ----------
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/freebsd/sys/contrib/device-tree/Bindings/leds/backlight/
H A Dti,lm3509.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrick Gansterer <paroga@paroga.com>
23 "#address-cells":
26 "#size-cells":
29 reset-gpios:
32 ti,brightness-rate-of-change-us:
36 ti,oled-mode:
49 The control register that is used to program the two current sinks.
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H A Dlm3630a-backlight.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/lm3630a-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI LM3630A High-Efficiency Dual-String White LED
10 - Lee Jones <lee@kernel.org>
11 - Daniel Thompson <daniel.thompson@linaro.org>
12 - Jingoo Han <jingoohan1@gmail.com>
15 The LM3630A is a current-mode boost converter which supplies the power and
26 '#address-cells':
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/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-ampere-mtmitchell.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/gpio/aspeed-gpio.h>
12 compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
27 * i2c bus 30-31 assigned to OCP slot 0-1
33 * i2c bus 32-33 assigned to Riser slot 0-1
39 * i2c bus 38-39 assigned to FRU on Riser slot 0-1
82 stdout-path = &uart5;
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H A Daspeed-bmc-ampere-mtjade.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
12 * i2c bus 50-57 assigned to NVMe slot 0-7
24 * i2c bus 60-67 assigned to NVMe slot 8-15
36 * i2c bus 70-77 assigned to NVMe slot 16-23
48 * i2c bus 80-81 assigned to NVMe M2 slot 0-1
60 stdout-path = &uart5;
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-osd3358-sm-red.dts1 //SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/
4 * This program is free software; you can redistribute it and/or modify
9 /dts-v1/;
12 #include "am335x-osd335x-common.dtsi"
13 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/display/tda998x.h>
18 model = "Octavo Systems OSD3358-SM-RED";
19 compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
23 regulator-min-microvolt = <1800000>;
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dwarp.dts4 * Copyright (c) 2008-2009 PIKA Technologies
8 * License version 2. This program is licensed "as is" without
12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
34 clock-frequency = <0>; /* Filled in by zImage */
35 timebase-frequency = <0>; /* Filled in by zImage */
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H A Dhotfoot.dts4 * Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
7 * License version 2. This program is licensed "as is" without
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by zImage */
36 timebase-frequency = <0>; /* Filled in by zImage */
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-supply = <&ppvar_sys>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&ap_edp_bklten>;
37 /* FIXED REGULATORS - parents above children */
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/freebsd/sys/dev/usb/net/
H A Dif_axe.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999, 2000-2003
18 * 4. Neither the name of the author nor the names of any co-contributors
53 * and has a 64-bit multicast hash filter. There is some information
57 * - You must set bit 7 in the RX control register, otherwise the
59 * - You must initialize all 3 IPG registers, or you won't be able
312 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); in axe_cmd()
324 locked = mtx_owned(&sc->sc_mtx); in axe_miibus_readreg()
355 locked = mtx_owned(&sc->sc_mtx); in axe_miibus_writereg()
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_mci.c73 if (!(ah->ah_config.ath_hal_mci_config & in ar9300_mci_osla_setup()
80 thresh = MS(ah->ah_config.ath_hal_mci_config, in ar9300_mci_osla_setup()
147 time_out -= 10; in ar9300_mci_wait_for_interrupt()
219 if ((ahp->ah_mci_coex_bt_version_known == AH_FALSE) && in ar9300_mci_send_coex_version_query()
220 (ahp->ah_mci_bt_state != MCI_BT_SLEEP)) { in ar9300_mci_send_coex_version_query()
238 ahp->ah_mci_coex_major_version_wlan; in ar9300_mci_send_coex_version_response()
240 ahp->ah_mci_coex_minor_version_wlan; in ar9300_mci_send_coex_version_response()
248 u_int32_t *payload = &ahp->ah_mci_coex_wlan_channels[0]; in ar9300_mci_send_coex_wlan_channels()
250 if ((ahp->ah_mci_coex_wlan_channels_update == AH_TRUE) && in ar9300_mci_send_coex_wlan_channels()
251 (ahp->ah_mci_bt_state != MCI_BT_SLEEP)) in ar9300_mci_send_coex_wlan_channels()
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/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2010-2015 Broadcom Corporation
10 * distributed with the Asus RT-N16 firmware source code release.
77 /* siba backplane configuration broadcast (siba-only) */
81 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */
97 #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */
100 /* clock control registers (non-PMU devices) */
114 #define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* "slowclock" (rev 6-9) */
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
9 * This program is free software; you can redistribute it and/or
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
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/freebsd/sys/dev/bxe/
H A Dbxe_elink.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
970 * elink_check_lfa - This function checks if link reinitialization is required,
982 struct bxe_softc *sc = params->sc; in elink_check_lfa()
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/freebsd/sys/contrib/dev/acpica/
H A Dchanges.txt1 ----------------------------------------
6 Fix 2 critical CVE addressing memory leaks - Seunghun Han
17 ----------------------------------------
30 ----------------------------------------
35 …that the PHAT firmware health record offset works correctly, fix various sub-table offsets, preven…
37 Fix the optional table 4-byte signature. Contributed by: Daniil Tatianin <99danilt@gmail.com>
56 ----------------------------------------
71 Add new tables for various architectures/OS, mainly RISC-V and also update many more.
73 Add an option to either make the output deterministic or non-deterministic.
80 ----------------------------------------
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