| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | datasource.json | 15 …"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local cor…
20 …"BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 du…
30 …"BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory…
60 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
65 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
70 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
75 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
80 …"BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local…
85 …"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local cor…
90 …"BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local…
[all …]
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-remoteproc | 4 Description: Remote processor firmware
7 remote processor.
9 To change the running firmware, ensure the remote processor is
15 Description: Remote processor state
17 Reports the state of the remote processor, which will be one of:
25 "offline" means the remote processor is powered off.
27 "suspended" means that the remote processor is suspended and
30 "running" is the normal state of an available remote processor
33 the remote processor.
35 "invalid" is returned if the remote processor is in an
[all …]
|
| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local…
[all …]
|
| H A D | frontend.json | 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
114 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e…
[all …]
|
| H A D | other.json | 371 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
372 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
377 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
378 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
383 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
384 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
389 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
390 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…
395 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to either de…
396 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
[all …]
|
| /linux/drivers/eisa/ |
| H A D | eisa.ids | 74 AIR1001 "AIR P6NDP PCI/EISA Dual-Pentium Processor System Board"
84 ALR3000 "80486 Processor Module"
85 ALR3010 "Pentium Processor Board"
91 ALRB0A0 "Primary System Processor Board - 80486DX2/66"
92 ALRB0B0 "Secondary System Processor Board - 80486DX2/66"
245 CPQ5000 "Compaq 386/33 System Processor Board used as Secondary"
246 CPQ5251 "Compaq 5/133 System Processor Board-2MB"
247 CPQ5253 "Compaq 5/166 System Processor Board-2MB"
248 CPQ5255 "Compaq 5/133 System Processor Board-1MB"
249 CPQ525D "Compaq 5/100 System Processor Board-1MB"
[all …]
|
| /linux/Documentation/arch/powerpc/ |
| H A D | elf_hwcaps.rst | 80 The processor is PowerPC 601.
93 The processor is 40x or 44x family.
97 The processor has a unified L1 cache for instructions and data, as
99 Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
112 This is a 601 specific HWCAP, so if it is known that the processor
118 The processor is POWER4 or PPC970/FX/MP.
122 The processor is POWER5.
125 The processor is POWER5+.
128 The processor is Cell.
131 The processor implements the embedded category ("BookE") architecture.
[all …]
|
| /linux/arch/m68k/ |
| H A D | Kconfig.cpu | 2 comment "Processor Type"
10 the full 68000 processor instruction set.
12 of the 68000 processor family. They are mainly targeted at embedded
15 processor instruction set.
17 MC68xxx processor, select M68KCLASSIC.
19 processor, select COLDFIRE.
77 processor, say Y. Otherwise, say N. Note that the 68020 requires a
89 processor, say Y. Otherwise, say N. Note that a MC68EC030 will not
98 or MC68040 processor, say Y. Otherwise, say N. Note that an
108 processor, say Y. Otherwise, say N.
[all …]
|
| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,omap-remoteproc.yaml | 13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
22 sub-system. The DSP processor sub-system can contain any of the TI's C64x,
23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
27 Each remote processor sub-system is represented as a single DT node. Each node
29 the host processor (MPU) to perform the device management of the remote
30 processor and to communicate with the remote processor. The various properties
54 for this remote processor to access any external RAM memory or
[all …]
|
| /linux/arch/arm/include/asm/ |
| H A D | proc-fns.h | 23 struct processor { struct
33 * Set up any processor specifics argument
37 * Check for processor bugs argument
41 * Disable any processor specifics argument
49 * Idle the processor argument
53 * Processor architecture specific
82 static inline void init_proc_vtable(const struct processor *p) in init_proc_vtable() argument
103 extern struct processor processor;
113 extern struct processor *cpu_vtable[];
116 static inline void init_proc_vtable(const struct processor *p) in init_proc_vtable()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | cache.json | 72 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the …
239 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data for…
245 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data for…
250 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data …
256 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data …
261 …mand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.",
267 …refetch) that true miss for the L2 cache with a snoop miss in the other processor module. Require…
294 … or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data for…
300 … or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data for…
305 … or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | data-fabric.json | 4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
[all …]
|
| /linux/tools/power/cpupower/man/ |
| H A D | cpupower-monitor.1 | 3 cpupower\-monitor \- Report processor frequency and idle statistics
18 \fBcpupower-monitor \fP reports processor topology, frequency and idle power
22 \fBcpupower-monitor \fP implements independent processor sleep state and
42 The name and a description of each counter and its processor hierarchy level
50 [P] \-> Processor Package (Socket)
101 state it is also used to show C0 (processor is active) and Cx (processor is in
117 For example an IvyBridge processor has sleep state capabilities which got
118 introduced in Nehalem and SandyBridge processor families.
119 Thus on an IvyBridge processor one will get Nehalem and SandyBridge sleep
125 AMD laptop and desktop processor (family 12h and 14h) sleep state counters.
[all …]
|
| /linux/Documentation/hwmon/ |
| H A D | asc7621.rst | 117 - Monitors VCCP, 2.5V, 3.3V, 5.0V, and 12V motherboard/processor supplies
137 peci_legacy = 1, PECI Processor Temperature 0
141 4 PECI Processor Temperature 0
142 5 PECI Processor Temperature 1
143 6 PECI Processor Temperature 2
144 7 PECI Processor Temperature 3
153 4 PECI Processor Temperature 0
154 5 PECI Processor Temperature 1
155 6 PECI Processor Temperature 2
156 7 PECI Processor Temperature 3
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | uncore-cache.json | 147 … "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
156 "BriefDescription": "An external snoop hits a modified line in some processor core.",
165 …re snoop initiated by this Cbox due to processor core memory request which hits a modified line in…
174 …cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
183 "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
192 … snoop initiated by this Cbox due to processor core memory request which hits a non-modified line …
201 …fDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
210 "BriefDescription": "An external snoop misses in some processor core.",
219 …ross-core snoop initiated by this Cbox due to processor core memory request which misses in some p…
|
| /linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | uncore-cache.json | 147 … "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
156 "BriefDescription": "An external snoop hits a modified line in some processor core.",
165 …re snoop initiated by this Cbox due to processor core memory request which hits a modified line in…
174 …cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
183 "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
192 … snoop initiated by this Cbox due to processor core memory request which hits a non-modified line …
201 …fDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
210 "BriefDescription": "An external snoop misses in some processor core.",
219 …ross-core snoop initiated by this Cbox due to processor core memory request which misses in some p…
|
| /linux/Documentation/admin-guide/acpi/ |
| H A D | cppc_sysfs.rst | 4 Collaborative Processor Performance Control (CPPC)
13 performance of a logical processor on a contiguous and abstract performance
40 * highest_perf : Highest performance of this processor (abstract scale).
41 * nominal_perf : Highest sustained performance of this processor
43 * lowest_nonlinear_perf : Lowest performance of this processor with nonlinear
45 * lowest_perf : Lowest performance of this processor (abstract scale).
49 The above frequencies should only be used to report processor performance in
54 Reference counter ticks up proportional to processor's reference performance.
55 Delivered counter ticks up proportional to processor's delivered performance.
|
| /linux/drivers/remoteproc/ |
| H A D | ti_sci_proc.h | 3 * Texas Instruments TI-SCI Processor Controller Helper Functions
15 * struct ti_sci_proc - structure representing a processor control client
19 * @proc_id: processor id for the consumer remoteproc device
63 dev_err(tsp->dev, "ti-sci processor request failed: %d\n", in ti_sci_proc_request()
74 dev_err(tsp->dev, "ti-sci processor release failed: %d\n", in ti_sci_proc_release()
85 dev_err(tsp->dev, "ti-sci processor handover of %d to %d failed: %d\n", in ti_sci_proc_handover()
99 dev_err(tsp->dev, "ti-sci processor set_config failed: %d\n", in ti_sci_proc_set_config()
111 dev_err(tsp->dev, "ti-sci processor set_control failed: %d\n", in ti_sci_proc_set_control()
125 dev_err(tsp->dev, "ti-sci processor get_status failed: %d\n", in ti_sci_proc_get_status()
|
| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | cache.json | 72 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the …
239 …ads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
245 …ads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
250 …s (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
256 …d & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Require…
294 …by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data for…
300 …by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data for…
305 … L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.",
311 …2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Require…
349 …sts (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 8 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
17 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
27 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
37 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
47 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
57 …s retired. Branch prediction predicts the branch target and enables the processor to begin executi…
67 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
77 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
87 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
97 …s retired. Branch prediction predicts the branch target and enables the processor to begin executi…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | uncore-cache.json | 147 … "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
156 "BriefDescription": "An external snoop hits a modified line in some processor core.",
165 …re snoop initiated by this Cbox due to processor core memory request which hits a modified line in…
174 …cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
183 "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
192 … snoop initiated by this Cbox due to processor core memory request which hits a non-modified line …
201 …fDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
210 "BriefDescription": "An external snoop misses in some processor core.",
219 …ross-core snoop initiated by this Cbox due to processor core memory request which misses in some p…
|
| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | special-register-buffer-data-sampling.rst | 22 A processor is affected by SRBDS if its Family_Model and stepping is
67 processor.
102 Setting IA32_MCU_OPT_CTRL[0] (RNGDS_MITG_DIS) to 1 for a logical processor
104 enclave on that logical processor. Opting out of the mitigation for a
105 particular logical processor does not affect the RDRAND and RDSEED mitigations
130 Not affected Processor not vulnerable
131 Vulnerable Processor vulnerable and mitigation disabled
132 Vulnerable: No microcode Processor vulnerable and microcode is missing
134 Mitigation: Microcode Processor is vulnerable and mitigation is in
136 Mitigation: TSX disabled Processor is only vulnerable when TSX is
[all …]
|
| H A D | gather_data_sampling.rst | 54 IA32_ARCH_CAPABILITIES[GDS_NO] R/O Processor is not vulnerable.
67 However, the processor will still enumerate AVX support. Userspace that
89 Not affected Processor not vulnerable.
90 Vulnerable Processor vulnerable and mitigation disabled.
91 Vulnerable: No microcode Processor vulnerable and microcode is missing
94 no microcode Processor is vulnerable and microcode is missing
96 Mitigation: Microcode Processor is vulnerable and mitigation is in
98 Mitigation: Microcode (locked) Processor is vulnerable and mitigation is in
101 hypervisor status Running on a virtual guest processor that is
103 processor is mitigated or vulnerable.
|
| /linux/tools/perf/pmu-events/arch/powerpc/power9/ |
| H A D | marked.json | 25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp…
80 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without c…
85 …"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the…
120 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
130 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a…
155 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
180 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor…
185 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
190 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…
[all …]
|
| /linux/Documentation/driver-api/pm/ |
| H A D | cpuidle.rst | 17 fetch and execute instructions: hardware threads, if present, or processor
20 with it, there is an opportunity to save energy for the processor that it
22 instructions from memory and putting some of the processor's functional units
27 (from the kernel perspective) and ask the processor to use (or "enter") that
35 units: *governors* responsible for selecting idle states to ask the processor
45 select an idle state to ask the processor to enter in order to save some energy.
86 processor holding the given CPU can be asked to enter).
113 Called to select an idle state for the processor holding the (logical)
125 the scheduler tick before asking the processor to enter the selected
128 processor will be asked to enter the selected idle state without
[all …]
|