processor\-local (full) in projects: linux

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Searched +full:processor +full:- +full:local (Results 1 – 25 of 286) sorted by relevance

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/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	cache.json	5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another … 11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", 35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … [all …]
H A D	frontend.json	47 "BriefDescription": "Number of I-ERAT reloads", 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a… 95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano… 101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di… 102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d… 107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on … 108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on… 113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an… [all …]
H A D	other.json	11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong … 113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re… 161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d… 167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d… 197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi… 203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi… 215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch … 221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch … 359 "BriefDescription": "IFU Finished a (non-branch) instruction", [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	datasource.json	10 …er this event counted only cacheable loads but in P10 both cacheable and non-cacheable loads are i… 15 …"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local cor… 20 …"BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 du… 30 …"BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory… 40 …"All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happ… 45 …All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happ… 50 … "All successful D-side store dispatches for this thread that were L2 hits. Since the event happen… 55 … missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 t… 60 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t… 65 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a … [all …]
H A D	marked.json	15 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel… 60 …n which the marked instruction is the oldest in the pipeline (next-to-finish or next-to-complete)." 95 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel… 125 …"BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory… 135 …"BriefDescription": "The processor's data cache was reloaded from a source other than the local co… 160 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel… 190 …": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores." 225 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel… 265 …"BriefDescription": "The processor's instruction cache was reloaded from beyond the local core's L… 270 …"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local cor…
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A D	data-fabric.json	4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.", 12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.", 20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.", 28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.", 36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.", 44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.", 52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.", 60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.", 68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.", 76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.", [all …]
H A D	recommended.json	4 "BriefDescription": "Execution-time branch misprediction ratio (non-speculative).", 150 "BriefDescription": "L1 demand data cache fills from local L2 cache.", 216 "BriefDescription": "Macro-ops dispatched.", 227 "BriefDescription": "Macro-ops retired.", 232 "BriefDescription": "DRAM read data for local processor.", 236 "ScaleUnit": "6.103515625e-5MiB" 240 "BriefDescription": "DRAM write data for local processor.", 244 "ScaleUnit": "6.103515625e-5MiB" 248 "BriefDescription": "DRAM read data for remote processor.", 252 "ScaleUnit": "6.103515625e-5MiB" [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A D	marked.json	10 …page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant mem… 25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp… 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 80 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without c… 85 …"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the… 110 …"BriefDescription": "Duration in cycles to reload from a location other than the local core's L3 d… 120 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on … 130 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 140 …A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a… [all …]
H A D	translation.json	5 "BriefDescription": "Processor cycles" 15 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor… 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed" 70 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 80 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 95 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 125 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an… 130 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)" 140 …"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this t… 145 …le Entry was loaded into the TLB from a memory location including L4 from local remote or distant … [all …]
H A D	pipeline.json	10 "BriefDescription": "Number of I-ERAT reloads" 25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 30 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a… 40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 135 …"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L… 145 …ead due to icache misses that were sourced from beyond the local L3. The source could be local/rem… 175 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch… 180 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… [all …]
H A D	other.json	45 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 65 "BriefDescription": "Read-write data cache collisions" 90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core" 95 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d… 145 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st… 200 "BriefDescription": "Read-write data cache collisions" 230 "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load" 255 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st… 280 …-word boundary, which causes it to require an additional slice than than what normally would be re… 290 "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet" [all …]
/linux/arch/mips/include/asm/octeon/
H A D	cvmx-scratch.h	7 * Copyright (c) 2003-2008 Cavium Networks 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 30 * This file provides support for the processor local scratch memory. 31 * Scratch memory is byte addressable - all addresses are byte addresses. 42 #define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 / 45 Reads an 8 bit value from the processor local scratchpad memory. 57 * Reads a 16 bit value from the processor local scratchpad memory. 69 * Reads a 32 bit value from the processor local scratchpad memory. 81 * Reads a 64 bit value from the processor local scratchpad memory. [all …]
/linux/Documentation/ABI/testing/
H A D	sysfs-bus-rpmsg	4 Contact: Ohad Ben-Cohen <ohad@wizery.com> 7 processor. Channels are identified with a (textual) name, 16 Contact: Ohad Ben-Cohen <ohad@wizery.com> 19 processor. Channels have a local ("source") rpmsg address, 26 This sysfs entry contains the src (local) rpmsg address 34 Contact: Ohad Ben-Cohen <ohad@wizery.com> 37 processor. Channels have a local ("source") rpmsg address, 48 remote processor. This make it a local rpmsg server, 56 Contact: Ohad Ben-Cohen <ohad@wizery.com> 59 processor. Channels are identified by a textual name (see [all …]
/linux/Documentation/devicetree/bindings/timer/
H A D	samsung,exynos4210-mct.yaml	1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzk@kernel.org> 14 global timer and CPU local timers. The global timer is a 64-bit free running 15 up-counter and can generate 4 interrupts when the counter reaches one of the 16 four preset counter values. The CPU local timers are 32-bit free running 17 down-counters and generate an interrupt when the counter expires. There is 18 one CPU local timer instantiated in MCT for every CPU in the system. [all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A D	intel,ce4100-lapic.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) 10 - Rahul Tanwar <rtanwar@maxlinear.com> 15 architecture design, with a local component (LAPIC) integrated 16 into the processor itself and an external I/O APIC. Local APIC 17 (lapic) receives interrupts from the processor's interrupt pins, 19 And it sends these to the processor core for handling. [all …]
H A D	intel,ce4100-ioapic.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rahul Tanwar <rtanwar@maxlinear.com> 15 architecture design, with a local component (LAPIC) integrated 16 into the processor itself and an external I/O APIC. Local APIC 17 (lapic) receives interrupts from the processor's interrupt pins, 19 And it sends these to the processor core for handling. 28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf [all …]
/linux/net/rxrpc/
H A D	conn_object.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 14 #include "ar-internal.h" 28 struct rxrpc_local *local = conn->local; in rxrpc_poke_conn() local 31 if (WARN_ON_ONCE(!local)) in rxrpc_poke_conn() 34 spin_lock_irq(&local->lock); in rxrpc_poke_conn() 35 busy = !list_empty(&conn->attend_link); in rxrpc_poke_conn() 38 list_add_tail(&conn->attend_link, &local->conn_attend_q); in rxrpc_poke_conn() 40 spin_unlock_irq(&local->lock); in rxrpc_poke_conn() 41 rxrpc_wake_up_io_thread(local); in rxrpc_poke_conn() 64 INIT_LIST_HEAD(&conn->cache_link); in rxrpc_alloc_connection() [all …]
/linux/kernel/
H A D	cpu_pm.c	1 // SPDX-License-Identifier: GPL-2.0-only 53 * cpu_pm_register_notifier - register a driver with cpu_pm 74 * cpu_pm_unregister_notifier - unregister a driver with cpu_pm 94 * cpu_pm_enter - CPU low power entry notifier 102 * co-processor, interrupt controller and its PM extensions, local CPU 115 * cpu_pm_exit - CPU low power exit notifier 120 * Notified drivers can include VFP co-processor, interrupt controller 121 * and its PM extensions, local CPU timers context save/restore which 133 * cpu_cluster_pm_enter - CPU cluster low power entry notifier 140 * domain. Notified drivers can include VFP co-processor, interrupt controller [all …]
/linux/Documentation/arch/x86/
H A D	intel-hfi.rst	1 .. SPDX-License-Identifier: GPL-2.0 4 Hardware-Feedback Interface for scheduling on Intel Hardware 8 -------- 11 IA-32 Architectures Software Developer's Manual (Intel SDM) Volume 3 Section 19 ------------------------------- 23 capability is given as a unit-less quantity in the range [0-255]. Higher values 30 at which these capabilities are updated is specific to each processor model. On 39 capabilities of a given logical processor becomes zero, it is an indication that 41 that processor for performance or energy efficiency reasons, respectively. 44 -------------------------------- [all …]
/linux/arch/mips/include/asm/
H A D	mips-gic.h	1 /* SPDX-License-Identifier: GPL-2.0-or-later / 8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h 29 / For read-only shared registers / 34 / For read-write shared registers / 39 / For read-only local registers / 44 / For read-write local registers / 49 / For read-only shared per-interrupt registers / 62 / For read-write shared per-interrupt registers / 81 / For read-only local per-interrupt registers / 88 / For read-write local per-interrupt registers */ [all …]
/linux/Documentation/devicetree/bindings/cpu/
H A D	idle-states.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 - Anup Patel <anup@brainfault.org> 15 1 - Introduction 18 ARM and RISC-V systems contain HW capable of managing power consumption 19 dynamically, where cores can be put in different low-power states (ranging 21 representing the range of dynamic idle states that a processor can enter at [all …]
/linux/Documentation/devicetree/bindings/arm/stm32/
H A D	st,mlahb.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 ML-AHB interconnect 10 - Fabien Dessenne <fabien.dessenne@foss.st.com> 11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects 15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory 17 using different buses (see [2]): balancing the Cortex-M firmware accesses 23 - $ref: /schemas/simple-bus.yaml# [all …]
/linux/arch/powerpc/include/asm/nohash/
H A D	tlbflush.h	1 /* SPDX-License-Identifier: GPL-2.0 / 8 - flush_tlb_mm(mm) flushes the specified mm context TLB's 9 * - flush_tlb_page(vma, vmaddr) flushes one page 10 * - local_flush_tlb_mm(mm, full) flushes the specified mm context on 11 * the local processor 12 * - local_flush_tlb_page(vma, vmaddr) flushes one page on the local processor 13 * - flush_tlb_range(vma, start, end) flushes a range of pages 14 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages 29 #define MMU_NO_CONTEXT ((unsigned int)-1) 37 unsigned int pid = READ_ONCE(mm->context.id); in local_flush_tlb_mm() [all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A D	thead,th1520-mbox.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mailbox/thead,th1520-mbox.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: T-head TH1520 Mailbox Controller 10 The T-head mailbox controller enables communication and coordination between 12 through mailbox channels. It also allows one core to signal another processor 16 - Michal Wilczynski <m.wilczynski@samsung.com> 20 const: thead,th1520-mbox 24 - description: Clock for the local mailbox [all …]
/linux/drivers/firmware/efi/
H A D	cper-x86.c	1 // SPDX-License-Identifier: GPL-2.0 120 "Local Processor originated request", 121 "Local Processor responded to request", 122 "Local Processor observed", 145 "32-bit Mode Execution Context", 146 "64-bit Mode Execution Context", 148 "32-bit Mode Debug Registers (DR0-DR7)", 149 "64-bit Mode Debug Registers (DR0-DR7)", 169 print_bool("Processor Context Corrupt", pfx, check, CHECK_MS_PCC); in print_err_info_ms() 220 print_bool("Processor Context Corrupt", pfx, check, CHECK_PCC); in print_err_info() [all …]

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