processor\-a\-side (full) in projects: freebsd

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Searched +full:processor +full:- +full:a +full:- +full:side (Results 1 – 25 of 206) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A D	fsl,mu-msi.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <Frank.Li@nxp.com> 16 for one processor (A side) to signal the other processor (B side) using 20 different clocks (from each side of the different peripheral buses). 21 Therefore, the MU must synchronize the accesses from one side to the 23 registers (Processor A-side, Processor B-side). 28 - $ref: /schemas/interrupt-controller/msi-controller.yaml# [all …]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	frontend.json	5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct… 41 "BriefDescription": "Cycles when a demand ifetch was pending", 47 "BriefDescription": "Number of I-ERAT reloads", 53 "BriefDescription": "IERAT Reloaded (Miss) for a 16M page", 60 "PublicDescription": "IERAT Reloaded (Miss) for a 4k page" 65 "BriefDescription": "IERAT Reloaded (Miss) for a 64k page", 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a… 95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano… [all …]
H A D	other.json	11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong … 83 …"BriefDescription": "Pairable BC+8 branch that has not been converted to a Resolve Finished in the… 89 …"BriefDescription": "Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipe… 113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re… 161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d… 167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d… 197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi… 203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi… 215 …anch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-for… [all …]
H A D	cache.json	5 …e processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a dif… 6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another … 11 …he processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a diff… 12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch… 17 …riefDescription": "The processor's data cache was reloaded from another chip's L4 on a different N… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", 35 …"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local… [all …]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	translation.json	5 "BriefDescription": "Processor cycles" 15 …BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core… 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed" 25 …escription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same No… 35 …A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on th… 45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin… 50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)" 60 …A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a … 65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi… 70 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … [all …]
H A D	marked.json	5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n… 10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 20 …Description": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's… 25 …riefDescription": "The processor's data cache was reloaded from another chip's memory on the same … 35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp… 45 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's … 50 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's … 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 70 …iption": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO … 80 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without c… [all …]
H A D	pipeline.json	10 "BriefDescription": "Number of I-ERAT reloads" 15 …te that this count is per slice, so if a load spans multiple slices this event will increment mult… 25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 30 …scription": "The processor's data cache was reloaded either shared or modified data from another c… 35 …ription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node o… 40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 80 …ription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L… 90 …riefDescription": "The processor's data cache was reloaded from another chip's L4 on a different N… 95 …escription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core'… 100 …rbitration onto the issue pipe to another instruction (from the same thread or a different thread)" [all …]
H A D	other.json	30 "BriefDescription": "IERAT reloaded (after a miss) for 4K pages" 45 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 50 …cription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's … 55 …"BriefDescription": "A Conditional Branch that resolved to taken was mispredicted as not taken (du… 60 …"BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The strea… 65 "BriefDescription": "Read-write data cache collisions" 80 …"BriefDescription": "Cycles in which no new instructions can be dispatched to the ICT after a flus… 85 …"BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cac… 90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core" 95 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d… [all …]
H A D	cache.json	5 …ion": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set" 10 … allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks … 15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi… 20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p… 25 …n cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load" 35 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and… 40 …"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data… 45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its … 50 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the … 55 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… [all …]
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A D	fsl,mu.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dong Aisheng <aisheng.dong@nxp.com> 16 for one processor to signal the other processor using interrupts. 19 different clocks (from each side of the different peripheral buses). 20 Therefore, the MU must synchronize the accesses from one side to the 22 registers (Processor A-facing, Processor B-facing). 27 - const: fsl,imx6sx-mu 28 - const: fsl,imx7ulp-mu [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/
H A D	cache.json	8 …a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requ… 17 …a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to me… 22 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 37 …a full or near full condition which likely indicates back pressure from the intra-die interconnect… 56 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line… 68 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit… 80 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the … 140 …that data was in the process of being brought into the L1 cache. Typically a load will receive th… 152 …"PublicDescription": "Counts the number of memory uops retired that is either a loads or a store o… 188 …ee the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memo… [all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A D	qcom,smp2p.txt	`4 a single 32-bit value between two processors. Each value has a single writer 5 (the local side) and a single reader (the remote side). Values are uniquely 6 identified in the system by the directed edge (local processor ID to remote 7 processor ID) and a string identifier. 9 - compatible: 15 - interrupts: 17 Value type: <prop-encoded-array> 20 - mboxes: 22 Value type: <prop-encoded-array> 26 - qcom,ipc: [all …]`
H A D	qcom,smp2p.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andy Gross <agross@kernel.org> 11 - Bjorn Andersson <bjorn.andersson@linaro.org> 12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 16 of a single 32-bit value between two processors. Each value has a single 17 writer (the local side) and a single reader (the remote side). Values are 18 uniquely identified in the system by the directed edge (local processor ID to 19 remote processor ID) and a string identifier. [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A D	cache.json	10 …a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requ… 21 …a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to me… 26 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 45 …a full or near full condition which likely indicates back pressure from the intra-die interconnect… 68 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line… 81 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit… 94 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the … 159 …that data was in the process of being brought into the L1 cache. Typically a load will receive th… 172 …"PublicDescription": "Counts the number of memory uops retired that is either a loads or a store o… 211 …ee the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memo… [all …]
H A D	pipeline.json	140 …branch instructions retired, where the target address taken was not what the processor predicted.", 152 … supposed to be taken and when it was not supposed to be taken (but the processor predicted the op… 164 …t call or near indirect jmp, where the target address taken was not what the processor predicted.", 176 …branch instructions retired, where the return address taken was not what the processor predicted.", 188 …Met) branch instructions retired that were supposed to be taken but the processor predicted that i… 199 …a halt state. The core enters the halt state when it is running the HLT instruction. In mobile sy… 211 …"PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable gene… 222 …"PublicDescription": "Reference cycles when core is not halted. This event uses a (_P)rogrammable… 233 …a halt state. The core enters the halt state when it is running the HLT instruction. In mobile sy… 238 "BriefDescription": "Cycles a divider is busy", [all …]
/freebsd/share/man/man4/
H A D	ix.4	`1 .\" Copyright (c) 2001-2008, Intel Corporation 20 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 .Bd -ragged -offset indent 47 Alternatively, to load the driver as a 50 .Bd -literal -offset indent 79 .Bl -bullet -compact 101 .Bl -tag -width "hw.ix.allow_unsupported_sfp" 109 Enable Message Signalled Interrupts (MSI-X). 111 Allow unsupported small form-factor pluggable 121 Enable Receive-Side Scaling (RSS). [all …]`
H A D	ntb_hw_amd.4	16 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 .Nd AMD Non-Transparent Bridge driver 35 .Bd -ragged -offset indent 40 Or, to load the driver as a module at boot, place the following line in 42 .Bd -literal -offset indent 47 .Bl -ohang 58 driver provides support for the Non-Transparent Bridge (NTB) hardware in 59 AMD EPYC processor family. 60 The Non-Transparent Bridge does not look as a regular PCI bridge, but as PCI 62 The driver hides details of hardware on the other side, but exposes memory windows, [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A D	memory.json	5 …"BriefDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an u… 11 …n": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.", 34 …increment represents an eight-byte access, although the instruction may only be accessing a portio… 39 "BriefDescription": "LS MAB allocates by type - DC prefetcher.", 45 "BriefDescription": "LS MAB allocates by type - stores.", 51 "BriefDescription": "LS MAB allocates by type - loads.", 63 "BriefDescription": "L1 DTLB Miss of a page of 1G size.", 69 "BriefDescription": "L1 DTLB Miss of a page of 2M size.", 75 "BriefDescription": "L1 DTLB Miss of a page of 32K size.", 81 "BriefDescription": "L1 DTLB Miss of a page of 4K size.", [all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A D	arm,coresight-dummy-source.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 specification and can be connected in various topologies to suit a particular 19 there would be Coresight source trace components on sub-processor which 20 are connected to AP processor via debug bus. For these devices, a dummy driver 27 side for dummy source component. 30 - Mike Leach <mike.leach@linaro.org> 31 - Suzuki K Poulose <suzuki.poulose@arm.com> [all …]
H A D	arm,coresight-dummy-sink.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 specification and can be connected in various topologies to suit a particular 19 Qualcomm platforms. It is a mini-USB hub implemented to support the USB-based 20 debug and trace capabilities. For this device, a dummy driver is needed to 21 register it as Coresight sink device in kernel side, so that path can be 23 coresight link of AP processor. It provides Coresight API for operations on 28 side for dummy sink component. [all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A D	st,stm32-rproc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 remote processor controller 14 - Fabien Dessenne <fabien.dessenne@foss.st.com> 15 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 19 const: st,stm32mp1-m4 24 processor. 31 reset-names: [all …]`
/freebsd/share/doc/smm/06.nfs/
H A D	1.t	21 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 Not Quite NFS (NQNFS) are kernel resident, but make use of a few system 43 the client side. 47 If the connection breaks, the client will attempt a reconnect with a new 49 The client side can operate without any daemons running, but performance 50 will be improved by running nfsiod daemons that perform read-aheads 51 and write-behinds. 52 For the server side to function, the daemons portmap, mountd and 56 Upon startup and after a hangup signal, mountd reads the exports 60 Mountd handles remote mount protocol (RFC1094, Appendix A) requests. [all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A D	cpm.txt	`1 * Freescale Communications Processor Module 10 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe". 11 - reg : A 48-byte region beginning with CPCR. 15 #address-cells = <1>; 16 #size-cells = <1>; 17 #interrupt-cells = <2>; 18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; 24 - fsl,cpm-command : This value is ORed with the opcode and command flag 25 to specify the device on which a CPM command operates. 27 - fsl,cpm-brg : Indicates which baud rate generator the device [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A D	memory.json	5 …-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (S… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 30 …"BriefDescription": "Retired lock instructions. Bus lock when a locked operations crosses a cache … 46 …"BriefDescription": "Dispatch of a single op that performs a load from and store to the same memor… 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full." 90 …increment represents an eight-byte access, although the instruction may only be accessing a portio… 119 …Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die.", 149 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB.", 155 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB.", [all …]
/freebsd/lib/libpmc/
H A D	pmc.3	1 .\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved. 14 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 37 provides a programming interface that allows applications to use 39 specific processes or for the system as a whole. 40 The library is implemented using the lower-level facilities offered by 46 using a software abstraction. 50 .Bl -bullet 53 These PMCs measure events in a whole-system manner, i.e., independent 57 Non-privileged process are allowed to allocate system scope PMCs if the 61 is non-zero. [all …]

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