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/linux/Documentation/devicetree/bindings/firmware/
H A Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx Network Processing Engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
29 - description: NPE0 (NPE-A) register range
[all …]
/linux/Documentation/netlabel/
H A Dcipso_ipv4.rst2 NetLabel CIPSO/IPv4 Protocol Engine
12 The NetLabel CIPSO/IPv4 protocol engine is based on the IETF Commercial
15 (draft-ietf-cipso-ipsecurity-01.txt). While the IETF draft never made
16 it to an RFC standard it has become a de-facto standard for labeled
19 Outbound Packet Processing
22 The CIPSO/IPv4 protocol engine applies the CIPSO IP option to packets by
31 Inbound Packet Processing
34 The CIPSO/IPv4 protocol engine validates every CIPSO IP option it finds at the
44 The CIPSO/IPv4 protocol engine contains a mechanism to translate CIPSO security
56 CIPSO/IPv4 protocol engine supports this caching mechanism.
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Dpipeline.json21 "PublicDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy",
24 "BriefDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy"
27 … all slots in the load-store issue queue are busy. This event counts the cycles where all slots in…
30 … all slots in the load-store issue queue are busy. This event counts the cycles where all slots in…
33 …ots in the data processing issue queue are busy. This event counts the cycles where all slots in t…
36 …ots in the data processing issue queue are busy. This event counts the cycles where all slots in t…
39 …tion for which all slots in the data engine issue queue are busy. This event is set every time tha…
42 …tion for which all slots in the data engine issue queue are busy. This event is set every time tha…
/linux/Documentation/devicetree/bindings/media/
H A Dti,vpe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DRA7x Video Processing Engine (VPE)
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
13 The Video Processing Engine (VPE) is a key component for image post
14 processing applications. VPE consist of a single memory to memory
20 const: ti,dra7-vpe
24 - description: The VPE main register region
[all …]
H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
17 processing, it successfully generates a corrected output image.
18 The engine can be used to perform scaling, cropping and pixel format
24 - nxp,imx8mp-dw100
[all …]
H A Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Video Decoder Engine
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
[all …]
/linux/Documentation/admin-guide/media/
H A Dplatform-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
17 am437x-vpfe TI AM437x VPFE
18 aspeed-video Aspeed AST2400 and AST2500
19 atmel-isc ATMEL Image Sensor Controller (ISC)
20 atmel-isi ATMEL Image Sensor Interface (ISI)
24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
26 coda-vpu Chips&Media Coda multi-standard codec IP
29 exynos-fimc-is EXYNOS4x12 FIMC-IS (Imaging Subsystem)
30 exynos-fimc-lite EXYNOS FIMC-LITE camera interface
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-ope.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ope.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Output Processing Engine (OPE) is one of the AHUB client. It has
12 sub blocks for data processing.
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Mohan Kumar <mkumard@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
20 - $ref: dai-common.yaml#
[all …]
H A Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
14 engine through ADMAIF.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
[all …]
H A Dnvidia,tegra210-mbdrc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-mbdrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 Processing Engine (OPE) which interfaces with Audio Hub (AHUB) via
16 - Jon Hunter <jonathanh@nvidia.com>
17 - Mohan Kumar <mkumard@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
23 - const: nvidia,tegra210-mbdrc
24 - items:
[all …]
H A Dnvidia,tegra210-peq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-peq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 PEQ sits inside Output Processing Engine (OPE) which interfaces
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Mohan Kumar <mkumard@nvidia.com>
19 - Sameer Pujar <spujar@nvidia.com>
24 - const: nvidia,tegra210-peq
25 - items:
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
H A Dpipeline.json15 "PublicDescription": "Duration for which all slots in the Load-Store Unit are busy",
18 "BriefDescription": "Duration for which all slots in the Load-Store Unit are busy"
21 "PublicDescription": "Duration for which all slots in the load-store issue queue are busy",
24 "BriefDescription": "Duration for which all slots in the load-store issue queue are busy"
27 … "PublicDescription": "Duration for which all slots in the data processing issue queue are busy",
30 … "BriefDescription": "Duration for which all slots in the data processing issue queue are busy"
33 "PublicDescription": "Duration for which all slots in the Data Engine issue queue are busy",
36 "BriefDescription": "Duration for which all slots in the Data Engine issue queue are busy"
/linux/Documentation/devicetree/bindings/crypto/
H A Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx cryptographic engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
21 const: intel,ixp4xx-crypto
23 intel,npe-handle:
[all …]
/linux/drivers/dma/amd/ptdma/
H A Dptdma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * -- Based on the CCP driver
25 #include "../../virt-dma.h"
94 #define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \
96 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
109 #define LSB_COUNT (LSB_END - LSB_START + 1)
124 * struct pt_passthru_engine - pass-through operation
133 * - bit_mod, byte_swap, src, dst, src_len
134 * - mask, mask_len if bit_mod is not PT_PASSTHRU_BITWISE_NOOP
145 * struct pt_cmd - PTDMA operation request
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dintel,ixp4xx-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
18 Processing Engine) and the IXP4xx Queue Manager to process
24 const: intel,ixp4xx-ethernet
30 queue-rx:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
[all …]
/linux/drivers/crypto/gemini/
H A Dsl3516-ce.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
8 * Called either Crypto Acceleration Engine Module, Security Acceleration Engine
9 * or IPSEC module in the datasheet, it will be called Crypto Engine for short
17 #include <crypto/engine.h>
90 * struct sl3516_ce_descriptor - descriptor for CE operations
100 * struct desc_frame_ctrl - Information for the current descriptor
107 * @perr: Protocol error during processing this descriptor
108 * @derr: Data error during processing this descriptor
125 * struct desc_flag_status - flag for this descriptor
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Dxlnx,sd-fec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cvetic, Dragan <dragan.cvetic@amd.com>
11 - Erim, Salih <salih.erim@amd.com>
14 The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
15 which provides high-throughput LDPC and Turbo Code implementations.
17 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
18 principally covers codes used by LTE. The FEC Engine offers significant
[all …]
/linux/drivers/dma/
H A Dsun4i-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/dma-mapping.h>
22 #include "virt-dma.h"
92 #define SUN4I_DDMA_PARA_DST_DATA_BLK_SIZE(n) (((n) - 1) << 24)
93 #define SUN4I_DDMA_PARA_DST_WAIT_CYCLES(n) (((n) - 1) << 16)
94 #define SUN4I_DDMA_PARA_SRC_DATA_BLK_SIZE(n) (((n) - 1) << 8)
95 #define SUN4I_DDMA_PARA_SRC_WAIT_CYCLES(n) (((n) - 1) << 0)
130 #define SUN4I_NDMA_NR_MAX_VCHANS (29 * 2 - 1)
137 #define SUNIV_NDMA_NR_MAX_VCHANS (24 * 2 - 1)
197 struct sun4i_dma_promise *processing; member
[all …]
/linux/Documentation/hid/
H A Dintel-thc-hid.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - A natively half-duplex Quad I/O capable SPI master
11 - Low latency I2C interface to support HIDI2C compliant devices
12 - A HW sequencer with RW DMA capability to system memory
29 -------------------------------
31 Below diagram illustrates the high-level architecture of THC software/hardware stack, which is fully
36 ----------------------------------------------
37 | +-----------------------------------+ |
39 | +-----------------------------------+ |
40 | +-----------------------------------+ |
[all …]
/linux/include/linux/
H A Dccp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 * ccp_present - check if a CCP device is present
29 * Returns zero if a CCP device is present, -ENODEV otherwise.
34 #define CCP_VMASK ((unsigned int)((1 << CCP_VSIZE) - 1))
39 * ccp_version - get the version of the CCP
46 * ccp_enqueue_cmd - queue an operation for processing by the CCP
55 * result in a return code of -EBUSY.
61 * will be -EINPROGRESS. Any other "err" value during callback is
65 * the return code is -EINPROGRESS or
66 * the return code is -EBUSY and CCP_CMD_MAY_BACKLOG flag is set
[all …]
/linux/include/dt-bindings/memory/
H A Dtegra186-mc.h119 /* High-definition audio (HDA) reads */
126 /* Reads from Cortex-A9 4 CPU cores via the L2 cache */
131 /* High-definition audio (HDA) writes */
133 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */
181 /* Audio Processing (APE) engine reads */
183 /* Audio Processing (APE) engine writes */
/linux/drivers/crypto/
H A Dhifn_795x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/dma-mapping.h>
73 * Processing Unit Registers (offset from BASEREG0)
75 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
76 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
77 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
78 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
79 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
80 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
85 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
[all …]
H A Dsa2ul.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2020 Texas Instruments Incorporated - http://www.ti.com
62 ((ctx_sz) ? ((ctx_sz) / 32 - 1) : 0)
70 /* Next Engine Select code in CP_ACE */
71 #define SA_ENG_ID_EM1 2 /* Enc/Dec engine with AES/DEC core */
73 #define SA_ENG_ID_AM1 4 /* Auth. engine with SHA1/MD5/SHA2 core */
74 #define SA_ENG_ID_AM2 5 /* Authentication engine for pass 2 */
80 #define SA_CMDL_OFFSET_NESC 0 /* Next Engine Select Code */
81 #define SA_CMDL_OFFSET_LABEL_LEN 1 /* Engine Command Label Length */
82 /* 16-bit Length of Data to be processed */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Drunl.c41 id = engn->func->cxid(engn, &cgid); in nvkm_engn_cgrp_get()
46 chan = nvkm_runl_chan_get_chid(engn->runl, id, pirqflags); in nvkm_engn_cgrp_get()
48 cgrp = chan->cgrp; in nvkm_engn_cgrp_get()
50 cgrp = nvkm_runl_cgrp_get_cgid(engn->runl, id, pirqflags); in nvkm_engn_cgrp_get()
60 struct nvkm_fifo *fifo = runl->fifo; in nvkm_runl_rc()
68 /* Runlist is blocked before scheduling recovery - fetch count. */ in nvkm_runl_rc()
69 BUG_ON(!mutex_is_locked(&runl->mutex)); in nvkm_runl_rc()
70 rc = atomic_xchg(&runl->rc_pending, 0); in nvkm_runl_rc()
76 state = atomic_cmpxchg(&cgrp->rc, NVKM_CGRP_RC_PENDING, NVKM_CGRP_RC_RUNNING); in nvkm_runl_rc()
87 if (runl->func->preempt) { in nvkm_runl_rc()
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8195-ipe.c1 // SPDX-License-Identifier: GPL-2.0-only
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
6 #include "clk-gate.h"
7 #include "clk-mtk.h"
9 #include <dt-bindings/clock/mt8195-clk.h>
10 #include <linux/clk-provider.h>
37 .compatible = "mediatek,mt8195-ipesys",
49 .name = "clk-mt8195-ipe",
55 MODULE_DESCRIPTION("MediaTek MT8195 Image Processing Engine clocks driver");

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