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/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processin
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/freebsd/crypto/openssl/doc/man3/
H A DSSL_set_async_callback.pod11 - manage asynchronous operations
29 objects generated based on this B<SSL_CTX> will get this callback. If an engine
31 B<SSL_MODE_ASYNC> has been set and an asynchronous capable engine completes a
37 asynchronous B<SSL> object, so that when an engine completes a cryptography
44 SSL_get_async_status() returns the engine status. This function facilitates the
45 communication from the engine to the application. During an SSL session,
46 cryptographic operations are dispatched to an engine. The engine status is very
48 dispatched. If the engine does not support this additional callback method,
67 OpenSSL submits the asynchronous request to the engine. If a retry occurs at
73 The OpenSSL engine pauses the current job and returns, so that the
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H A DSSL_CTX_set_split_send_fragment.pod11 SSL_SESSION_get_max_fragment_length - Control fragment size settings and pipelining operations
36 capability could be utilised to parallelise the processing of a single
42 In order to benefit from the pipelining capability. You need to have an engine
43 that provides ciphers that support this. The OpenSSL "dasync" engine provides
44 AES128-SHA based ciphers that have this capability. However, these are for
51 functions will only accept a value in the range 512 - SSL3_RT_MAX_PLAIN_LENGTH.
56 used (i.e. normal non-parallel operation). The number of pipelines set must be
57 in the range 1 - SSL_MAX_PIPELINES (32). Setting this to a value > 1 will also
61 engine.
73 SSL_write/SSL_write_ex called with 0-2000 bytes == 1 pipeline used
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/freebsd/sys/dev/safe/
H A Dsafereg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
33 * Register definitions for SafeNet SafeXcel-1141 crypto device.
47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */
50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
51 #define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */
52 #define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */
53 #define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */
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/freebsd/secure/lib/libcrypto/man/man3/
H A DSSL_set_async_callback.318 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
98 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
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H A DENGINE_add.318 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
98 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
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/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/
H A Dpipeline.json21 "PublicDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy",
24 "BriefDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy"
27 … all slots in the load-store issue queue are busy. This event counts the cycles where all slots in…
30 … all slots in the load-store issue queue are busy. This event counts the cycles where all slots in…
33 …ots in the data processing issue queue are busy. This event counts the cycles where all slots in t…
36 …ots in the data processing issue queue are busy. This event counts the cycles where all slots in t…
39 …tion for which all slots in the data engine issue queue are busy. This event is set every time tha…
42 …tion for which all slots in the data engine issue queue are busy. This event is set every time tha…
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Drenesas,vsp1.txt1 * Renesas VSP Video Processing Engine
3 The VSP is a video processing engine that supports up-/down-scaling, alpha
4 blending, color space conversion and various other image processing features.
5 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
9 - compatible: Must contain one of the following values
10 - "renesas,vsp1" for the R-Car Gen2 and RZ/G1 VSP1
11 - "renesas,vsp2" for the R-Car Gen3 and RZ/G2 VSP2
13 - reg: Base address and length of the registers block for the VSP.
14 - interrupts: VSP interrupt specifier.
15 - clocks: A phandle + clock-specifier pair for the VSP functional clock.
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H A Dti,vpe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DRA7x Video Processing Engine (VPE)
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
13 The Video Processing Engine (VPE) is a key component for image post
14 processing applications. VPE consist of a single memory to memory
20 const: ti,dra7-vpe
24 - description: The VPE main register region
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H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
17 processing, it successfully generates a corrected output image.
18 The engine can be used to perform scaling, cropping and pixel format
24 - nxp,imx8mp-dw100
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H A Dnvidia,tegra-vde.txt1 NVIDIA Tegra Video Decoder Engine
4 - compatible : Must contain one of the following values:
5 - "nvidia,tegra20-vde"
6 - "nvidia,tegra30-vde"
7 - "nvidia,tegra114-vde"
8 - "nvidia,tegra124-vde"
9 - "nvidia,tegra132-vde"
10 - reg : Must contain an entry for each entry in reg-names.
11 - reg-names : Must include the following entries:
12 - sxe
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H A Drenesas,vsp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VSP Video Processing Engine
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The VSP is a video processing engine that supports up-/down-scaling, alpha
14 blending, color space conversion and various other image processing features.
15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
20 - enum:
21 - renesas,r9a07g044-vsp2 # RZ/G2L
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H A Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Video Decoder Engine
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
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/freebsd/sys/dev/safexcel/
H A Dsafexcel_reg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
73 #define AIC_POL_CTRL(x) (0xE000 - ((x) << 12))
74 #define AIC_TYPE_CTRL(x) (0xE004 - ((x) << 12))
75 #define AIC_ENABLE_CTRL(x) (0xE008 - ((x) << 12))
76 #define AIC_RAW_STAL(x) (0xE00C - ((x) << 12))
77 #define AIC_ENABLE_SET(x) (0xE00C - ((x) << 12))
78 #define AIC_ENABLED_STAT(x) (0xE010 - ((x) << 12))
79 #define AIC_ACK(x) (0xE010 - ((x) << 12))
80 #define AIC_ENABLE_CLR(x) (0xE014 - ((x) << 12))
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/freebsd/contrib/bearssl/inc/
H A Dbearssl_ssl.h51 * registry](http://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml#tls-parameters-4).
54 * a fatal alert message is sent of received, then the SSL engine context
66 /** \brief Optimal buffer size for monodirectional engine
70 /** \brief Optimal buffer size for bidirectional engine
93 * Implementation note: SSL-level error codes should be in the 1..31
101 /** \brief SSL status: caller-provided parameter is incorrect. */
135 regards to the current engine state. */
230 * \brief Decryption engine for SSL.
232 * When processing incoming records, the SSL engine will use a decryption
233 * engine that uses a specific context structure, and has a set of
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H A Dbearssl_x509.h41 * # X.509 Certificate Chain Processing
43 * An X.509 processing engine receives an X.509 chain, chunk by chunk,
47 * is thus injected in the engine in SSL order (end-entity first).
49 * The engine's job is to return the public key to use for SSL/TLS.
51 * engine.
53 * **The "known key" engine** returns a public key which is already known
54 * from out-of-band information (e.g. the client _remembers_ the key from
56 * engine since it simply ignores the chain, thereby avoiding the need
59 * **The "minimal" engine** implements minimal X.509 decoding and chain
62 * - The provided chain should validate "as is". There is no attempt
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra210-ope.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ope.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Output Processing Engine (OPE) is one of the AHUB client. It has
12 sub blocks for data processing.
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Mohan Kumar <mkumard@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
20 - $ref: dai-common.yaml#
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H A Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
14 engine through ADMAIF.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
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/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a73/
H A Dpipeline.json15 "PublicDescription": "Duration for which all slots in the Load-Store Unit are busy",
18 "BriefDescription": "Duration for which all slots in the Load-Store Unit are busy"
21 "PublicDescription": "Duration for which all slots in the load-store issue queue are busy",
24 "BriefDescription": "Duration for which all slots in the load-store issue queue are busy"
27 … "PublicDescription": "Duration for which all slots in the data processing issue queue are busy",
30 … "BriefDescription": "Duration for which all slots in the data processing issue queue are busy"
33 "PublicDescription": "Duration for which all slots in the Data Engine issue queue are busy",
36 "BriefDescription": "Duration for which all slots in the Data Engine issue queue are busy"
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx cryptographic engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
21 const: intel,ixp4xx-crypto
23 intel,npe-handle:
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/freebsd/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DExprEngine.h1 //===- ExprEngine.h - Path-Sensitive Expression-Level Dataflow --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines a meta-engine for path-sensitive dataflow analysis that
13 //===----------------------------------------------------------------------===//
99 /// compute the this-region correctly.
109 /// This call is a constructor for a temporary that is lifetime-extended
110 /// by binding it to a reference-type field within an aggregate,
114 /// This call is a pre-C++17 elidable constructor that we failed to elide
128 /// The modes of inlining, which override the default analysis-wide settings.
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/freebsd/crypto/openssl/engines/
H A De_afalg.c2 * Copyright 2016-2024 The OpenSSL Project Authors. All Rights Reserved.
21 #include <openssl/engine.h>
34 # warning "AFALG ENGINE requires Kernel Headers >= 4.1.0"
35 # warning "Skipping Compilation of AFALG engine"
79 static int afalg_destroy(ENGINE *e);
80 static int afalg_init(ENGINE *e);
81 static int afalg_finish(ENGINE *e);
84 static int afalg_ciphers(ENGINE *e, const EVP_CIPHER **cipher,
93 /* Engine Id and Name */
95 static const char *engine_afalg_name = "AFALG engine suppor
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dintel,ixp4xx-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
18 Processing Engine) and the IXP4xx Queue Manager to process
24 const: intel,ixp4xx-ethernet
30 queue-rx:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
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/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dxlnx,sd-fec.txt3 The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
4 which provides high-throughput LDPC and Turbo Code implementations.
6 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
7 principally covers codes used by LTE. The FEC Engine offers significant
12 - compatible: Must be "xlnx,sd-fec-1.1"
13 - clock-names : List of input clock names from the following:
14 - "core_clk", Main processing clock for processing core (required)
15 - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
16 - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
17 - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
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/freebsd/sys/dev/hifn/
H A Dhifn7751reg.h3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
9 * Copyright (c) 2000-2001 Network Security Technologies, Inc.
12 * Please send any comments, feedback, bug-fixes, or feature requests to
41 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
77 * The values below should multiple of 4 -- and be large enough to handle
81 * mac-key + rc4-key
112 * Processing Unit Registers (offset from BASEREG0)
114 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
115 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
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