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Searched full:prescale (Results 1 – 23 of 23) sorted by relevance

/freebsd/sys/dev/sdhci/
H A Dsdhci_fsl_fdt.c319 uint32_t prescale, div, val32, div_ratio; in fsl_sdhc_fdt_set_clock() local
333 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, slot->clock, prescale, div); in fsl_sdhc_fdt_set_clock()
335 div_ratio = prescale * div; in fsl_sdhc_fdt_set_clock()
345 prescale = 4; in fsl_sdhc_fdt_set_clock()
348 prescale = 4; in fsl_sdhc_fdt_set_clock()
351 prescale = 4; in fsl_sdhc_fdt_set_clock()
358 sc->div_ratio = prescale * div; in fsl_sdhc_fdt_set_clock()
361 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n", in fsl_sdhc_fdt_set_clock()
362 slot->clock, sc->baseclk_hz / (prescale * div), in fsl_sdhc_fdt_set_clock()
363 sc->baseclk_hz, prescale, div); in fsl_sdhc_fdt_set_clock()
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H A Dfsl_sdhci.c570 uint32_t divisor, freq, prescale, val32; in fsl_sdhc_set_clock() local
622 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) in fsl_sdhc_set_clock()
623 prescale <<= 1; in fsl_sdhc_set_clock()
625 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) in fsl_sdhc_set_clock()
630 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n", in fsl_sdhc_set_clock()
631 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, in fsl_sdhc_set_clock()
632 prescale, divisor); in fsl_sdhc_set_clock()
638 prescale >>= 1; in fsl_sdhc_set_clock()
643 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; in fsl_sdhc_set_clock()
/freebsd/sys/arm/freescale/imx/
H A Dimx_gpt.c141 uint32_t basefreq, prescale, setup_ticks, t1, t2; in imx_gpt_attach() local
218 prescale = 0; in imx_gpt_attach()
221 prescale = basefreq / TARGET_FREQUENCY; in imx_gpt_attach()
222 sc->clkfreq = basefreq / prescale; in imx_gpt_attach()
223 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ in imx_gpt_attach()
225 WRITE4(sc, IMX_GPT_PR, prescale); in imx_gpt_attach()
/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dmax6650.txt13 - maxim,fan-prescale : Pre-scaling value, as per datasheet [1]. Lower values
26 maxim,fan-prescale = <4>;
H A Dmaxim,max6650.yaml35 maxim,fan-prescale:
67 maxim,fan-prescale = <4>;
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dcirrus,clps711x-fb.txt12 - ac-prescale : LCD AC bias frequency. This frequency is the required
31 ac-prescale = <17>;
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dcirrus,ep9307-keypad.yaml45 cirrus,prescale:
/freebsd/sys/contrib/device-tree/src/arm/cirrus/
H A Dep7211-edb7211.dts29 ac-prescale = <17>;
/freebsd/sys/dev/ic/
H A Dns16550.h109 #define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE"
/freebsd/sys/arm/ti/
H A Dti_i2c.c100 uint8_t psc; /* Fast/Standard mode prescale divider */
125 * In all cases we prescale the clock to 24MHz as recommended in the manual.
/freebsd/sys/i386/i386/
H A Dgeode.c203 * We run MFGPT0 off the 32kHz frequency and prescale by 16384 giving a
/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_rtc.h142 uint32_t tmr_prsc; /* 0x00a8 timer prescale */
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h42 #define AR_TOPS 0x0044 /* timeout prescale count */
343 #define AR_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
H A Dar5211_reset.c671 * Prescale these values to remove 64-bit operation requirement at the loss in ar5211PerCalibrationN()
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h47 #define AR_TOPS 0x0044 /* Timeout prescale register */
H A Dar5210_reset.c179 OS_REG_WRITE(ah, AR_TOPS, 8); /* timeout prescale */ in ar5210Reset()
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h37 #define AR_TOPS 0x0044 /* MAC timeout prescale count */
382 #define AR_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
H A Dar5212_reset.c1029 * Prescale these values to remove 64-bit operation in ar5212PerCalibrationN()
/freebsd/sys/powerpc/mpc85xx/
H A Dlbc.c484 * - set bus monitor timing and timer prescale in lbc_attach()
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h146 /* MAC timeout prescale count */
148 #define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale
/freebsd/sys/arm/ti/cpsw/
H A Dif_cpsw.c2637 /* Set the prescale to produce 4us pulses from the 125 Mhz clock. */ in cpsw_intr_coalesce()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp25328 int Prescale = Mask.size() / ScaledMask.size(); in combineShuffleToZeroExtendVectorInReg() local
25331 EltSizeInBits *= Prescale; in combineShuffleToZeroExtendVectorInReg()
/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h8200 …prescale = 2**2 of clock periods (~16ns) b001 : prescale = 2**3 of clock periods b010 : prescale =…