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/linux/Documentation/devicetree/bindings/hwmon/
H A Dmoortec,mr75203.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
19 *) Temperature Sensor (TS) - used to monitor core temperature (e.g. mr74137).
20 *) Voltage Monitor (VM) - used to monitor voltage levels (e.g. mr74138).
21 *) Process Detector (PD) - used to assess silicon speed (e.g. mr74139).
22 *) Delay Chain - ring oscillator connected to the PD, used to measure IO
25 *) Pre Scaler - provides divide-by-X scaling of input voltage, which can then
26 be presented for VM for measurement within its range (e.g. mr76006 -
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/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Register definition file for Samsung G-Scaler driver
12 /* G-Scaler enable */
18 /* G-Scaler S/W reset */
22 /* G-Scaler IRQ */
29 /* G-Scaler input control */
65 /* G-Scaler source image size */
70 /* G-Scaler source image offset */
75 /* G-Scaler cropped source image size */
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H A Dgsc-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * header file for Samsung EXYNOS5 SoC series G-Scaler driver
20 #include <media/videobuf2-v4l2.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/videobuf2-dma-contig.h>
27 #include "gsc-regs.h"
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/linux/drivers/gpu/drm/exynos/
H A Dregs-gsc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* linux/drivers/gpu/drm/exynos/regs-gsc.h
7 * Register definition file for Samsung G-Scaler driver
13 /* G-Scaler enable */
33 /* G-Scaler S/W reset */
37 /* G-Scaler IRQ */
45 /* G-Scaler input control */
91 /* G-Scaler source image size */
98 /* G-Scaler source image offset */
105 /* G-Scaler cropped source image size */
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H A Dregs-fimc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-fimc.h
52 /* Pre-scaler control 1 */
54 /* Pre-scaler control 2 */
56 /* Main scaler control */
300 (EXYNOS_CIOYSA5 + ((__x) - DEF_PP) * 4))
304 (EXYNOS_CIOCBSA5 + ((__x) - DEF_PP) * 4))
308 (EXYNOS_CIOCRSA5 + ((__x) - DEF_PP) * 4))
506 /* Main scaler control register */
H A Dexynos_drm_gsc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #include "regs-gsc.h"
29 * GSC stands for General SCaler and
30 * supports image scaler/rotator and input/output DMA operations.
65 #define gsc_read(offset) readl(ctx->regs + (offset))
66 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
69 * A structure of scaler.
72 * @pre_shfactor: pre sclaer shift factor.
75 * @main_hratio: the main scaler's horizontal ratio.
76 * @main_vratio: the main scaler's vertical ratio.
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/linux/drivers/hwmon/
H A Dmr75203.c1 // SPDX-License-Identifier: GPL-2.0
111 #define PVT_TEMP_MIN_mC -40000
117 #define PVT_SERIES5_J_CONST -100
133 * struct voltage_device - VM single input parameters.
136 * @pre_scaler: Pre scaler value (1 or 2) used to normalize the voltage output
139 * The structure provides mapping between channel-number (0..N-1) to VM-index
140 * (0..num_vm-1) and channel-index (0..ch_num-1) where N = num_vm * ch_num.
150 * struct voltage_channels - VM channel count.
188 struct pvt_device *pvt = file->private_data; in pvt_ts_coeff_j_read()
192 len = scnprintf(buf, sizeof(buf), "%d\n", pvt->ts_coeff.j); in pvt_ts_coeff_j_read()
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/linux/drivers/gpu/drm/meson/
H A Dmeson_vpp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * - Postblend, Blends the OSD1 only
23 * - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
25 * - Intermediate FIFO with default Amlogic values
29 * - Preblend for video overlay pre-scaling
30 * - OSD2 support for cursor framebuffer
31 * - Video pre-scaling before postblend
32 * - Full Vertical/Horizontal OSD scaling to support TV overscan
33 * - HDR conversion
38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
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/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include "camif-core.h"
15 #include <media/drv-intf/s3c_camif.h>
19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
65 #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id))
77 /* CICOTRGFMT, CIPRTRGFMT - Target format */
100 /* xBURSTn - 5-bits width */
110 /* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */
113 /* CICOSCPREDST, CIPRSCPREDST. Pre-scaler control 2. */
116 /* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */
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/linux/drivers/watchdog/
H A Dlpc18xx_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * -----
9 * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit
35 /* Clock pre-scaler */
70 spin_lock_irqsave(&lpc18xx_wdt->lock, flags); in lpc18xx_wdt_feed()
71 writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); in lpc18xx_wdt_feed()
72 writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED); in lpc18xx_wdt_feed()
73 spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags); in lpc18xx_wdt_feed()
81 struct watchdog_device *wdt_dev = &lpc18xx_wdt->wdt_dev; in lpc18xx_wdt_timer_feed()
86 mod_timer(&lpc18xx_wdt->timer, jiffies + in lpc18xx_wdt_timer_feed()
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/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_connector.h103 } scaler; member
113 bool scaler:1; member
147 * even on pre-nv50 where we do not support atomic. This embedded
165 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) in nouveau_connector_is_mst()
172 encoder = &nv_encoder->base.base; in nouveau_connector_is_mst()
173 return encoder->encoder_type == DRM_MODE_ENCODER_DPMST; in nouveau_connector_is_mst()
183 struct drm_device *dev = nv_crtc->base.dev; in nouveau_crtc_connector_get()
191 if (connector->encoder && connector->encoder->crtc == crtc) { in nouveau_crtc_connector_get()
/linux/Documentation/devicetree/bindings/input/
H A Dcirrus,ep9307-keypad.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/cirrus,ep9307-keypad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
13 - $ref: /schemas/input/matrix-keymap.yaml#
16 The KPP is designed to interface with a keypad matrix with 2-point contact
17 or 3-point contact keys. The KPP is designed to simplify the software task
24 - const: cirrus,ep9307-keypad
25 - items:
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/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
23 * This driver configures the 2 16/32-bit count-up timers as follows:
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
34 * obtained from device tree. The pre-scaler of 32 is used.
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
60 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
67 * struct ttc_timer - This definition defines local timer structure
105 * ttc_set_interval - Set the timer interval value
115 /* Disable the counter, set the counter value and re-enable counter */ in ttc_set_interval()
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H A Dtimer-keystone.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Keystone broadcast clock-event
17 #define TIMER_NAME "timer-keystone"
121 evt->event_handler(evt); in keystone_timer_interrupt()
153 return -EINVAL; in keystone_timer_init()
159 return -ENXIO; in keystone_timer_init()
182 /* reset timer as 64-bit, no pre-scaler, plus features are disabled */ in keystone_timer_init()
205 event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; in keystone_timer_init()
206 event_dev->set_next_event = keystone_set_next_event; in keystone_timer_init()
207 event_dev->set_state_shutdown = keystone_shutdown; in keystone_timer_init()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h3 * Copyright (c) 2007-2008 Intel Corporation
66 /* these are outputs from the chip - integrated only
84 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
100 * create the DMA scatter-gather list for each FB color plane. This sg
112 * in the rotated and remapped GTT view all no-CCS formats (up to 2
216 * state. This must be called _after_ display->get_pipe_config has
217 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
459 * When it rolls over re-auth has to be triggered.
467 * over re-Auth has to be triggered.
520 state of connector->polled in case hotplug storm detection changes it */
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H A Dintel_crtc_state_dump.c1 // SPDX-License-Identifier: MIT
20 "hd=%d hb=%d-%d hs=%d-%d ht=%d, " in intel_dump_crtc_timings()
21 "vd=%d vb=%d-%d vs=%d-%d vt=%d, " in intel_dump_crtc_timings()
23 mode->crtc_clock, in intel_dump_crtc_timings()
24 mode->crtc_hdisplay, mode->crtc_hblank_start, mode->crtc_hblank_end, in intel_dump_crtc_timings()
25 mode->crtc_hsync_start, mode->crtc_hsync_end, mode->crtc_htotal, in intel_dump_crtc_timings()
26 mode->crtc_vdisplay, mode->crtc_vblank_start, mode->crtc_vblank_end, in intel_dump_crtc_timings()
27 mode->crtc_vsync_start, mode->crtc_vsync_end, mode->crtc_vtotal, in intel_dump_crtc_timings()
28 mode->flags); in intel_dump_crtc_timings()
39 m_n->data_m, m_n->data_n, in intel_dump_m_n_config()
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H A Dintel_sprite.c53 return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A'; in sprite_name()
69 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in chv_sprite_update_csc()
70 struct intel_display *display = to_intel_display(plane->base.dev); in chv_sprite_update_csc()
71 const struct drm_framebuffer *fb = plane_state->hw.fb; in chv_sprite_update_csc()
72 enum plane_id plane_id = plane->id; in chv_sprite_update_csc()
84 /* BT.601 full range YCbCr -> full range RGB */ in chv_sprite_update_csc()
87 -2925, 4096, -1410, in chv_sprite_update_csc()
90 /* BT.709 full range YCbCr -> full range RGB */ in chv_sprite_update_csc()
93 -1917, 4096, -767, in chv_sprite_update_csc()
97 const s16 *csc = csc_matrix[plane_state->hw.color_encoding]; in chv_sprite_update_csc()
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/linux/Documentation/admin-guide/media/
H A Dipu3.rst1 .. SPDX-License-Identifier: GPL-2.0
24 ImgU). The CIO2 driver is available as drivers/media/pci/intel/ipu3/ipu3-cio2*
36 Both of the drivers implement V4L2, Media Controller and V4L2 sub-device
38 MIPI CSI-2 interfaces through V4L2 sub-device sensor drivers.
44 interface to the user space. There is a video node for each CSI-2 receiver,
47 The CIO2 contains four independent capture channel, each with its own MIPI CSI-2
48 receiver and DMA engine. Each channel is modelled as a V4L2 sub-device exposed
49 to userspace as a V4L2 sub-device node and has two pads:
53 .. flat-table::
54 :header-rows: 1
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/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
54 /* 0 - selects Writeback A (LCD), 1 - selects Writeback B (LCD/ISP) */
59 /* 0 - ITU601; 1 - ITU709 */
114 /* Pre-scaler control 1 */
119 /* Main scaler control */
275 #define FIMC_REG_CSIIMGFMT_USER(x) (0x30 + x - 1)
326 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
335 writel(mask, dev->regs + FIMC_REG_CIFCNTSEQ); in fimc_hw_set_dma_seq()
/linux/drivers/gpu/drm/
H A Ddrm_blend.c43 * sub-pixel accuracy, which is scaled up to a pixel-aligned destination
96 * plane-wide opacity, from transparent (0) to opaque (0xffff). It can be
99 * pre-multiplied by the global alpha associated to the plane.
109 * "rotate-<degrees>":
113 * "reflect-<axis>":
117 * reflect-x::
120 * | | -> | |
123 * reflect-y::
126 * | | -> | |
137 * value can also be immutable, to inform userspace about the hard-coded
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/linux/drivers/clk/bcm/
H A Dclk-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0+
27 #include <linux/clk-provider.h>
38 #include <dt-bindings/clock/bcm2835.h>
45 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
253 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
337 writel(CM_PASSWORD | val, cprman->regs + reg); in cprman_write()
342 return readl(cprman->regs + reg); in cprman_read()
355 spin_lock(&cprman->regs_lock); in bcm2835_measure_tcnt_mux()
372 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n"); in bcm2835_measure_tcnt_mux()
383 dev_err(cprman->dev, "timeout waiting for !BUSY\n"); in bcm2835_measure_tcnt_mux()
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/linux/drivers/spi/
H A Dspi-ppc4xx.c1 // SPDX-License-Identifier: GPL-2.0-only
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
103 * CDM = (OPBCLK/4*SCPClkOut) - 1
143 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", in spi_ppc4xx_txrx()
144 t->tx_buf, t->rx_buf, t->len); in spi_ppc4xx_txrx()
146 hw = spi_controller_get_devdata(spi->controller); in spi_ppc4xx_txrx()
148 hw->tx = t->tx_buf; in spi_ppc4xx_txrx()
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
11 #include <linux/dma-buf.h>
32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
35 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
37 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
74 * struct dpu_plane - local dpu plane structure
101 struct msm_drm_private *priv = plane->dev->dev_private; in _dpu_plane_get_kms()
103 return to_dpu_kms(priv->kms); in _dpu_plane_get_kms()
107 * _dpu_plane_calc_bw - calculate bandwidth required for a plane
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/linux/drivers/staging/media/ipu3/include/uapi/
H A Dintel-ipu3.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (C) 2017 - 2018 Intel Corporation */
11 /* Vendor specific - used for IPU3 camera sub-system */
17 /* from include/uapi/linux/v4l2-controls.h */
26 #define IPU3_UAPI_GRID_START_MASK ((1 << 12) - 1)
34 * struct ipu3_uapi_grid_config - Grid plane config
56 * create a grid-based output, and the data is then divided into "slices".
71 * struct ipu3_uapi_awb_set_item - Memory layout for each cell in AWB
108 * struct ipu3_uapi_awb_raw_buffer - AWB raw buffer
119 * struct ipu3_uapi_awb_config_s - AWB config
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