Home
last modified time | relevance | path

Searched +full:pre +full:- +full:scaler (Results 1 – 25 of 31) sorted by relevance

12

/linux/Documentation/devicetree/bindings/hwmon/
H A Dmoortec,mr75203.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
19 *) Temperature Sensor (TS) - used to monitor core temperature (e.g. mr74137).
20 *) Voltage Monitor (VM) - used to monitor voltage levels (e.g. mr74138).
21 *) Process Detector (PD) - used to assess silicon speed (e.g. mr74139).
22 *) Delay Chain - ring oscillator connected to the PD, used to measure IO
25 *) Pre Scaler - provides divide-by-X scaling of input voltage, which can then
26 be presented for VM for measurement within its range (e.g. mr76006 -
[all …]
/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Register definition file for Samsung G-Scaler driver
12 /* G-Scaler enable */
18 /* G-Scaler S/W reset */
22 /* G-Scaler IRQ */
29 /* G-Scaler input control */
65 /* G-Scaler source image size */
70 /* G-Scaler source image offset */
75 /* G-Scaler cropped source image size */
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-gsc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* linux/drivers/gpu/drm/exynos/regs-gsc.h
7 * Register definition file for Samsung G-Scaler driver
13 /* G-Scaler enable */
33 /* G-Scaler S/W reset */
37 /* G-Scaler IRQ */
45 /* G-Scaler input control */
91 /* G-Scaler source image size */
98 /* G-Scaler source image offset */
105 /* G-Scaler cropped source image size */
[all …]
H A Dregs-fimc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-fimc.h
52 /* Pre-scaler control 1 */
54 /* Pre-scaler control 2 */
56 /* Main scaler control */
300 (EXYNOS_CIOYSA5 + ((__x) - DEF_PP) * 4))
304 (EXYNOS_CIOCBSA5 + ((__x) - DEF_PP) * 4))
308 (EXYNOS_CIOCRSA5 + ((__x) - DEF_PP) * 4))
506 /* Main scaler control register */
H A Dexynos_drm_gsc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #include "regs-gsc.h"
29 * GSC stands for General SCaler and
30 * supports image scaler/rotator and input/output DMA operations.
65 #define gsc_read(offset) readl(ctx->regs + (offset))
66 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
69 * A structure of scaler.
72 * @pre_shfactor: pre sclaer shift factor.
75 * @main_hratio: the main scaler's horizontal ratio.
76 * @main_vratio: the main scaler's vertical ratio.
[all …]
/linux/drivers/hwmon/
H A Dmr75203.c1 // SPDX-License-Identifier: GPL-2.0
111 #define PVT_TEMP_MIN_mC -40000
117 #define PVT_SERIES5_J_CONST -100
133 * struct voltage_device - VM single input parameters.
136 * @pre_scaler: Pre scaler value (1 or 2) used to normalize the voltage output
139 * The structure provides mapping between channel-number (0..N-1) to VM-index
140 * (0..num_vm-1) and channel-index (0..ch_num-1) where N = num_vm * ch_num.
150 * struct voltage_channels - VM channel count.
188 struct pvt_device *pvt = file->private_data; in pvt_ts_coeff_j_read()
192 len = scnprintf(buf, sizeof(buf), "%d\n", pvt->ts_coeff.j); in pvt_ts_coeff_j_read()
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_vpp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * - Postblend, Blends the OSD1 only
23 * - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
25 * - Intermediate FIFO with default Amlogic values
29 * - Preblend for video overlay pre-scaling
30 * - OSD2 support for cursor framebuffer
31 * - Video pre-scaling before postblend
32 * - Full Vertical/Horizontal OSD scaling to support TV overscan
33 * - HDR conversion
38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
[all …]
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include "camif-core.h"
15 #include <media/drv-intf/s3c_camif.h>
19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
65 #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id))
77 /* CICOTRGFMT, CIPRTRGFMT - Target format */
100 /* xBURSTn - 5-bits width */
110 /* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */
113 /* CICOSCPREDST, CIPRSCPREDST. Pre-scaler control 2. */
116 /* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */
[all …]
/linux/drivers/watchdog/
H A Dlpc18xx_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * -----
9 * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit
35 /* Clock pre-scaler */
70 spin_lock_irqsave(&lpc18xx_wdt->lock, flags); in lpc18xx_wdt_feed()
71 writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED); in lpc18xx_wdt_feed()
72 writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED); in lpc18xx_wdt_feed()
73 spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags); in lpc18xx_wdt_feed()
82 struct watchdog_device *wdt_dev = &lpc18xx_wdt->wdt_dev; in lpc18xx_wdt_timer_feed()
87 mod_timer(&lpc18xx_wdt->timer, jiffies + in lpc18xx_wdt_timer_feed()
[all …]
H A Ds3c2410_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
92 * DOC: Quirk flags for different Samsung watchdog IP-cores
97 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk
104 * write-only, writing any values to this register clears the interrupt, but
129 * %QUIRK_HAS_32BIT_CNT: WTDAT and WTCNT are 32-bit registers. With these
130 * 32-bit registers, larger values will be set, which means that larger timeouts
166 * struct s3c2410_wdt_variant - Per-variant config data
379 { .compatible = "google,gs101-wdt",
381 { .compatible = "samsung,s3c2410-wdt",
383 { .compatible = "samsung,s3c6410-wdt",
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_connector.h103 } scaler; member
113 bool scaler:1; member
147 * even on pre-nv50 where we do not support atomic. This embedded
165 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) in nouveau_connector_is_mst()
172 encoder = &nv_encoder->base.base; in nouveau_connector_is_mst()
173 return encoder->encoder_type == DRM_MODE_ENCODER_DPMST; in nouveau_connector_is_mst()
183 struct drm_device *dev = nv_crtc->base.dev; in nouveau_crtc_connector_get()
191 if (connector->encoder && connector->encoder->crtc == crtc) { in nouveau_crtc_connector_get()
/linux/Documentation/devicetree/bindings/input/
H A Dcirrus,ep9307-keypad.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/cirrus,ep9307-keypad.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
13 - $ref: /schemas/input/matrix-keymap.yaml#
16 The KPP is designed to interface with a keypad matrix with 2-point contact
17 or 3-point contact keys. The KPP is designed to simplify the software task
24 - const: cirrus,ep9307-keypad
25 - items:
[all …]
/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
23 * This driver configures the 2 16/32-bit count-up timers as follows:
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
34 * obtained from device tree. The pre-scaler of 32 is used.
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
60 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
67 * struct ttc_timer - This definition defines local timer structure
105 * ttc_set_interval - Set the timer interval value
115 /* Disable the counter, set the counter value and re-enable counter */ in ttc_set_interval()
[all …]
H A Dtimer-keystone.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Keystone broadcast clock-event
17 #define TIMER_NAME "timer-keystone"
121 evt->event_handler(evt); in keystone_timer_interrupt()
153 return -EINVAL; in keystone_timer_init()
159 return -ENXIO; in keystone_timer_init()
182 /* reset timer as 64-bit, no pre-scaler, plus features are disabled */ in keystone_timer_init()
205 event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; in keystone_timer_init()
206 event_dev->set_next_event = keystone_set_next_event; in keystone_timer_init()
207 event_dev->set_state_shutdown = keystone_shutdown; in keystone_timer_init()
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
54 /* 0 - selects Writeback A (LCD), 1 - selects Writeback B (LCD/ISP) */
59 /* 0 - ITU601; 1 - ITU709 */
114 /* Pre-scaler control 1 */
119 /* Main scaler control */
275 #define FIMC_REG_CSIIMGFMT_USER(x) (0x30 + x - 1)
326 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
335 writel(mask, dev->regs + FIMC_REG_CIFCNTSEQ); in fimc_hw_set_dma_seq()
/linux/drivers/spi/
H A Dspi-ppc4xx.c1 // SPDX-License-Identifier: GPL-2.0-only
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
103 * CDM = (OPBCLK/4*SCPClkOut) - 1
143 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", in spi_ppc4xx_txrx()
144 t->tx_buf, t->rx_buf, t->len); in spi_ppc4xx_txrx()
146 hw = spi_controller_get_devdata(spi->controller); in spi_ppc4xx_txrx()
148 hw->tx = t->tx_buf; in spi_ppc4xx_txrx()
[all …]
H A Dspi-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Mika Westerberg
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
21 #include <linux/dma-direction.h>
22 #include <linux/dma-mapping.h>
69 * struct ep93xx_spi - EP93xx SPI controller structure
75 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
99 #define bits_per_word_to_dss(bpw) ((bpw) - 1)
102 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
[all …]
/linux/drivers/rtc/
H A Drtc-sh.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH On-Chip RTC Support
5 * Copyright (C) 2006 - 2009 Paul Mundt
39 #define DRV_NAME "sh-rtc"
73 /* ALARM Bits - or with BCD encoded value */
84 #define RCR2_ADJ BIT(2) /* ADJustment (30-second) */
102 spin_lock(&rtc->lock); in sh_rtc_alarm()
104 tmp = readb(rtc->regbase + RCR1); in sh_rtc_alarm()
107 writeb(tmp, rtc->regbase + RCR1); in sh_rtc_alarm()
110 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); in sh_rtc_alarm()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/sspl/
H A Ddc_spl.c1 // SPDX-License-Identifier: MIT
51 int r0_x_end = r0->x + r0->width; in intersect_rec()
52 int r1_x_end = r1->x + r1->width; in intersect_rec()
53 int r0_y_end = r0->y + r0->height; in intersect_rec()
54 int r1_y_end = r1->y + r1->height; in intersect_rec()
56 rec.x = r0->x > r1->x ? r0->x : r1->x; in intersect_rec()
57 rec.width = r0_x_end > r1_x_end ? r1_x_end - rec.x : r0_x_end - rec.x; in intersect_rec()
58 rec.y = r0->y > r1->y ? r0->y : r1->y; in intersect_rec()
59 rec.height = r0_y_end > r1_y_end ? r1_y_end - rec.y : r0_y_end - rec.y; in intersect_rec()
80 if ((rec->x + adjust->x) >= 0) in spl_opp_adjust_rect()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_plane.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
11 #include <linux/dma-buf.h>
32 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
35 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
37 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
74 * struct dpu_plane - local dpu plane structure
101 struct msm_drm_private *priv = plane->dev->dev_private; in _dpu_plane_get_kms()
103 return to_dpu_kms(priv->kms); in _dpu_plane_get_kms()
107 * _dpu_plane_calc_bw - calculate bandwidth required for a plane
[all …]
/linux/drivers/scsi/sym53c8xx_2/
H A Dsym_hipd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * of PCI-SCSI IO processors.
6 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
9 * Copyright (C) 1998-2000 Gerard Roudier
12 * a port of the FreeBSD ncr driver to Linux-1.2.13.
16 * Stefan Esser <se@mi.Uni-Koeln.de>
24 *-----------------------------------------------------------------------------
75 #define sym_verbose (np->verbose)
131 * Asynchronous pre-scaler (ns). Shall be 40 for
153 #define SYM_MEM_CLUSTER_MASK (SYM_MEM_CLUSTER_SIZE-1)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
50 DPP_CLOCK_ENABLE, &s->is_enabled); in dpp30_read_state()
52 // Pre-degamma (ROM) in dpp30_read_state()
54 PRE_DEGAM_MODE, &s->pre_dgam_mode, in dpp30_read_state()
55 PRE_DEGAM_SELECT, &s->pre_dgam_select); in dpp30_read_state()
59 CM_GAMCOR_MODE_CURRENT, &s->gamcor_mode); in dpp30_read_state()
60 if (s->gamcor_mode) { in dpp30_read_state()
63 s->gamcor_mode = LUT_RAM_A; // Otherwise, LUT_RAM_B in dpp30_read_state()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v6_0.c94 (0x13830 - 0x7030) >> 2,
141 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
144 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
154 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
158 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
163 if (crtc >= adev->mode_info.num_crtc) in dce_v6_0_vblank_get_counter()
174 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_init()
175 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_init()
183 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_fini()
184 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_fini()
[all …]
H A Ddce_v8_0.c82 (0x13830 - 0x7030) >> 2,
129 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_rreg()
132 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_rreg()
142 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_wreg()
145 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_wreg()
150 if (crtc >= adev->mode_info.num_crtc) in dce_v8_0_vblank_get_counter()
161 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v8_0_pageflip_interrupt_init()
162 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v8_0_pageflip_interrupt_init()
170 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v8_0_pageflip_interrupt_fini()
171 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v8_0_pageflip_interrupt_fini()
[all …]

12