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/linux/drivers/cpuidle/
H A Dcpuidle-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <asm/pm-cps.h>
17 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
18 STATE_CLOCK_GATED, /* Core clock gated */
19 STATE_POWER_GATED, /* Core power gated */
36 if (cpus_are_siblings(0, dev->cpu) && (index > STATE_NC_WAIT)) in cps_nc_enter()
52 return -EINVAL; in cps_nc_enter()
55 /* Notify listeners the CPU is about to power down */ in cps_nc_enter()
57 return -EINTR; in cps_nc_enter()
78 .name = "nc-wait",
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/linux/Documentation/devicetree/bindings/power/
H A Dapple,pmgr-pwrstate.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC PMGR Power States
10 - Hector Martin <marcan@marcan.st>
13 - $ref: power-domain.yaml#
16 Apple SoCs include PMGR blocks responsible for power management,
17 which can control various clocks, resets, power states, and
18 performance features. This binding describes the device power
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/linux/arch/arm/mach-tegra/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
80 * The power up sequence of cold boot CPU and warm boot CPU in tegra30_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
103 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
104 * default. To power up the cold boot CPU, the power should in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
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H A Dsleep-tegra30.S1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
81 .arch armv7-a
192 * Puts the current CPU in wait-for-event mode on the flow controller
193 * and powergates it -- flags (in R0) indicate the request type.
196 * corrupts r0-r4, r10-r12
215 * Clear this CPU's "event" and "interrupt" flags and power gate
260 wfeeq @ CPU should be power gated here
293 * CPU power-gating process, to avoid loading from SDRAM which
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v13_0_4_ppsmc.h27 /*! @mainpage PMFW-PPS (PPLib) Message Interface
59 #define PPSMC_MSG_PowerDownVcn 0x06 ///< Power down VCN
60 #define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by defau…
88 #define PPSMC_MSG_SetPowerLimitPercentage 0x20 ///< Set power limit percentage
89 #define PPSMC_MSG_PowerDownJpeg 0x21 ///< Power down Jpeg
90 #define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by defa…
98 #define PPSMC_MSG_PowerDownIspByTile 0x29 ///< ISP is power gated by default
99 #define PPSMC_MSG_PowerUpIspByTile 0x2A ///< This message is used to power up ISP tile…
102 #define PPSMC_MSG_PowerDownUmsch 0x2D ///< Power down VCN.UMSCH (aka VSCH) scheduler
103 #define PPSMC_MSG_PowerUpUmsch 0x2E ///< Power up VCN.UMSCH (aka VSCH) scheduler
/linux/arch/mips/include/asm/
H A Dpm-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 * The CM & CPC can only handle coherence & power control on a per-core basis,
25 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
26 CPS_PM_CLOCK_GATED, /* Core clock gated */
27 CPS_PM_POWER_GATED, /* Core power gated */
32 * cps_pm_support_state - determine whether the system supports a PM state
40 * cps_pm_enter_state - enter a PM state
43 * Enter the given PM state. If coupled_coherence is non-zero then it is
45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32-rcc.txt6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
21 between gated clocks and other clocks and an index specifying the clock to
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H A Dmvebu-gated-clock.txt1 * Gated Clock bindings for Marvell EBU SoCs
4 peripheral clocks to be gated to save some power. The clock consumer
12 -----------------------------------
29 -----------------------------------
56 -----------------------------------
83 -----------------------------------
97 -----------------------------------
124 -----------------------------------
134 -----------------------------------
157 -----------------------------------
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/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
78 * throughput and memory controller power.
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
242 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */
533 /** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */
589 /** @brief GBE PLL hardware power sequencer */
599 /** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */
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/linux/drivers/staging/media/atomisp/pci/
H A Datomisp-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
56 * Enables the combining of adjacent 32-byte read requests to the same
57 * cache line. When cleared, each 32-byte read request is sent as a
64 * If cleared, the high speed clock going to the digital logic is gated when
65 * RCOMP update is happening. The clock is gated for a minimum of 100 nsec.
66 * If this bit is set, then the high speed clock is not gated during the
72 * Enables the combining of adjacent 32-byte write requests to the same
73 * cache line. When cleared, each 32-byte write request is sent as a
102 /* MRFLD ISP POWER related */
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
30 operating-points-v2: true
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/linux/drivers/mmc/host/
H A Dtoshsd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */
22 #define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
23 #define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
34 #define SD_PCICFG_PWR1_OFF 0x00 /* Turn off power */
/linux/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
9 There are 6 HW Power States:
10 0: POFF--Power Off
11 1: PDN--Power Down
12 2: CARDEMU--Card Emulation
13 3: ACT--Active Mode
14 4: LPS--Low Power State
15 5: SUS--Suspend
48 …LL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
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/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP2-specific DPLL control functions
16 #include "cm-regbits-24xx.h"
21 * _allow_idle - enable DPLL autoidle bits
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
25 * stop when its downstream clocks are gated. No return value.
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
31 if (!clk || !clk->dpll_data) in _allow_idle()
38 * _deny_idle - prevent DPLL from automatically idling
45 if (!clk || !clk->dpll_data) in _deny_idle()
/linux/arch/arm/include/asm/
H A Dmcpm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright: (C) 2012-2013 Linaro Limited
40 * branch once it is ready to re-enter the kernel using ptr, or NULL if it
41 * should be gated. A gated CPU is held in a WFE loop until its vector
55 * CPU/cluster power operations API for higher subsystems to use.
59 * mcpm_is_available - returns whether MCPM is initialized and available
66 * mcpm_cpu_power_up - make given CPU in given cluster runable
87 * mcpm_cpu_power_down - power the calling CPU down
92 * then the cluster is prepared for power-down too.
96 * On success this does not return. Re-entry in the kernel is expected
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/linux/arch/arm/mach-s3c/
H A Dcpuidle-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "regs-sys-s3c64xx.h"
20 #include "regs-syscon-power-s3c64xx.h"
47 .desc = "System active, ARM gated",
/linux/include/linux/pinctrl/
H A Dpinctrl-state.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * but not fully sleeping - some power may be on but clocks gated for
/linux/Documentation/devicetree/bindings/mfd/
H A Dmaxim,max77802.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Maxim MAX77802 Power Management IC
10 - Javier Martinez Canillas <javier@dowhile0.org>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 This is a part of device tree bindings for Maxim MAX77802 Power Management
17 The Maxim MAX77802 is a Power Management IC which includes voltage and
18 current regulators (10 high efficiency Buck regulators and 32 Low-DropOut
22 (gated/ungated) over I2C. The clock IDs are defined as preprocessor macros
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/linux/Documentation/arch/arm/sunxi/
H A Dclocks.rst11 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
49 A: The linux-sunxi wiki contains a page documenting the clock registers,
52 http://linux-sunxi.org/A10/CCM
57 https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn32/
H A Ddcn32_hubp.c2 * Copyright 2012-20 Advanced Micro Devices, Inc.
33 hubp2->hubp_regs->reg
36 hubp2->base.ctx
40 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
74 * For Pstate change using the MALL with sub-viewport buffering, in hubp32_prepare_subvp_buffering()
76 * and sub-viewport positioning by Display FW has to avoid the cursor in hubp32_prepare_subvp_buffering()
80 * Setting this should allow the sub-viewport position to always avoid the cursor because in hubp32_prepare_subvp_buffering()
81 * we do not allow the sub-viewport region to overlap with display prefetch (i.e. during blank). in hubp32_prepare_subvp_buffering()
97 * power gated, this wait would timeout. in hubp32_phantom_hubp_post_enable()
99 * we just wrote reg_val to non-0, if it stay 0 in hubp32_phantom_hubp_post_enable()
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/linux/sound/soc/sof/intel/
H A Dmtl.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
16 #include "../ipc4-priv.h"
19 #include "hda-ipc.h"
20 #include "../sof-audio.h"
49 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it, in mtl_ipc_dsp_done()
66 if (sdev->dspless_mode_selected) in mtl_dsp_check_ipc_irq()
100 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; in mtl_ipc_send_msg()
101 struct sof_ipc4_msg *msg_data = msg->msg_data; in mtl_ipc_send_msg()
104 hdev->delayed_ipc_tx_msg = msg; in mtl_ipc_send_msg()
108 hdev->delayed_ipc_tx_msg = NULL; in mtl_ipc_send_msg()
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/linux/sound/soc/intel/avs/
H A Dcnl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright(c) 2021-2024 Intel Corporation
15 const struct avs_spec *spec = adev->spec; in avs_cnl_ipc_interrupt()
18 snd_hdac_adsp_updatel(adev, spec->hipc->ctl_offset, in avs_cnl_ipc_interrupt()
21 hipc_ack = snd_hdac_adsp_readl(adev, spec->hipc->ack_offset); in avs_cnl_ipc_interrupt()
22 hipc_rsp = snd_hdac_adsp_readl(adev, spec->hipc->rsp_offset); in avs_cnl_ipc_interrupt()
25 if (hipc_ack & spec->hipc->ack_done_mask) { in avs_cnl_ipc_interrupt()
26 complete(&adev->ipc->done_completion); in avs_cnl_ipc_interrupt()
29 snd_hdac_adsp_updatel(adev, spec->hipc->ack_offset, spec->hipc->ack_done_mask, in avs_cnl_ipc_interrupt()
30 spec->hipc->ack_done_mask); in avs_cnl_ipc_interrupt()
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/linux/arch/arm/mach-lpc32xx/
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-lpc32xx/pm.c
12 * LPC32XX CPU and system power management
14 * The LPC32XX has three CPU modes for controlling system power: run,
15 * direct-run, and halt modes. When switching between halt and run modes,
16 * the CPU transistions through direct-run mode. For Linux, direct-run
25 * Direct-run mode:
32 * SYSCLK is gated off and the CPU and system clocks are halted.
36 * wake the system up back into direct-run mode.
41 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
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/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-brain.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron.dtsi"
10 #include "rk3288-veyron-broadcom-bluetooth.dtsi"
14 compatible = "google,veyron-brain-rev0", "google,veyron-brain",
17 vcc33_sys: vcc33-sys {
18 vin-supply = <&vcc_5v>;
22 compatible = "regulator-fixed";
23 regulator-name = "vcc33_io";
24 regulator-always-on;
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/linux/drivers/media/platform/nvidia/tegra-vde/
H A Dvde.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com>
10 #include <linux/dma-buf.h>
60 struct device *dev = vde->dev; in tegra_vde_alloc_bo()
66 return -ENOMEM; in tegra_vde_alloc_bo()
68 bo->vde = vde; in tegra_vde_alloc_bo()
69 bo->size = size; in tegra_vde_alloc_bo()
70 bo->dma_dir = dma_dir; in tegra_vde_alloc_bo()
71 bo->dma_attrs = DMA_ATTR_WRITE_COMBINE | in tegra_vde_alloc_bo()
74 if (!vde->domain) in tegra_vde_alloc_bo()
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