| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | qcom,wcd939x-sdw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd939x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
23 qcom,tx-port-mapping:
25 Specifies static port mapping between device and host tx ports.
26 In the order of the device port index.
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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| H A D | qcom,wcd938x-sdw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd938x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
24 qcom,tx-port-mapping:
26 Specifies static port mapping between slave and master tx ports.
27 In the order of slave port index.
28 $ref: /schemas/types.yaml#/definitions/uint32-array
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| /linux/drivers/net/dsa/microchip/ |
| H A D | ksz_dcb.c | 1 // SPDX-License-Identifier: GPL-2.0
13 /* Port X Control 0 register.
14 * The datasheet specifies: Port 1 - 0x10, Port 2 - 0x20, Port 3 - 0x30.
15 * However, the driver uses get_port_addr(), which maps Port 1 to offset 0.
61 /* ksz_supported_apptrust[] - Supported apptrust selectors and Priority Order
65 * the index within the array indicates the priority of the selector - lower
72 * non-configurable precedence where certain types of priority information
75 * 1. Tail Tag - Highest priority, overrides ACL, VLAN PCP, and DSCP priorities.
76 * 2. ACL - Overrides VLAN PCP and DSCP priorities.
77 * 3. VLAN PCP - Overrides DSCP priority.
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| H A D | lan937x_main.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
21 /* marker for ports without built-in PHY */
25 * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses.
27 * Each entry corresponds to a specific port on the LAN9370 switch,
28 * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and
29 * Port 5 is connected to an RGMII interface without a PHY. The values
33 [0] = 2, /* Port 1, T1 AFE0 */
34 [1] = 3, /* Port 2, T1 AFE1 */
35 [2] = 5, /* Port 3, T1 AFE3 */
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| /linux/drivers/net/ethernet/microchip/vcap/ |
| H A D | vcap_ag_api.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */
6 /* This file is autogenerated by cml-utils 2023-03-13 10:16:42 +0100.
63 * Used by 802.1BR Bridge Port Extension in an E-Tag
65 * Used by 802.1BR Bridge Port Extension in an E-Tag
67 * Set for frames containing an E-TAG (802.1BR Ethertype 893f)
69 * E-Tag group bits in 802.1BR Bridge Port Extension
71 * Used by 802.1BR Bridge Port Extension in an E-Tag
73 * Used by 802.1BR Bridge Port Extension in an E-Tag
78 * First DEI in multiple vlan tags (outer tag or default port tag)
86 * First PCP in multiple vlan tags (outer tag or default port tag)
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| /linux/drivers/net/ethernet/microchip/lan966x/ |
| H A D | lan966x_dcb.c | 1 // SPDX-License-Identifier: GPL-2.0+
40 for (int i = 0; i < conf->nselectors; i++) in lan966x_dcb_apptrust_contains()
41 if (conf->selectors[i] == selector) in lan966x_dcb_apptrust_contains()
51 struct lan966x_port *port = netdev_priv(dev); in lan966x_dcb_app_update() local
57 /* Get pcp ingress mapping */ in lan966x_dcb_app_update()
64 /* Get dscp ingress mapping */ in lan966x_dcb_app_update()
74 qos.default_prio = fls(qos.default_prio) - 1; in lan966x_dcb_app_update()
76 /* Get pcp rewrite mapping */ in lan966x_dcb_app_update()
83 qos.pcp_rewr.map[i] = fls(pcp_rewr_map.map[i]) - 1; in lan966x_dcb_app_update()
86 /* Get dscp rewrite mapping */ in lan966x_dcb_app_update()
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| /linux/include/linux/ |
| H A D | cb710.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright by Michał Mirosław, 2008-2009
21 /* per-virtual-slot structure */
28 /* per-device structure */
50 /* slot port accessors - so the logic is more clear in the code */
53 unsigned port, u##t value) \
55 iowrite##t(value, slot->iobase + port); \
59 unsigned port) \
61 return ioread##t(slot->iobase + port); \
65 unsigned port, u##t set, u##t clear) \
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| /linux/drivers/infiniband/core/ |
| H A D | iwpm_msg.c | 15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
42 * iwpm_valid_pid - Check if the userspace iwarp port mapper pid is valid
52 * iwpm_register_pid - Send a netlink query to userspace
53 * to get the iwarp port mapper pid
54 * @pm_msg: Contains driver info to send to the userspace port mapper
70 int ret = -EINVAL; in iwpm_register_pid()
80 nlh->nlmsg_seq = iwpm_get_nlmsg_seq(); in iwpm_register_pid()
81 nlmsg_request = iwpm_get_nlmsg_request(nlh->nlmsg_seq, nl_client, GFP_KERNEL); in iwpm_register_pid()
94 pm_msg->if_name, IWPM_NLA_REG_IF_NAME); in iwpm_register_pid()
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| /linux/Documentation/devicetree/bindings/display/imx/ |
| H A D | fsl,imx6q-ldb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The LVDS Display Bridge device tree node contains up to two lvds-channel
14 - Frank Li <Frank.Li@nxp.com>
19 - enum:
20 - fsl,imx53-ldb
21 - items:
22 - enum:
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| /linux/drivers/net/dsa/mv88e6xxx/ |
| H A D | global1.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
18 int addr = chip->info->global1_addr; in mv88e6xxx_g1_read()
25 int addr = chip->info->global1_addr; in mv88e6xxx_g1_write()
33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, in mv88e6xxx_g1_wait_bit()
40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, in mv88e6xxx_g1_wait_mask()
98 /* Returns 0 when done, -EBUSY when waiting, other negative codes on error */
106 dev_err(chip->dev, "Error reading status"); in mv88e6xxx_g1_is_eeprom_done()
116 return -EBUSY; in mv88e6xxx_g1_is_eeprom_done()
135 if (ret != -EBUSY) in mv88e6xxx_g1_wait_eeprom_done()
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| H A D | global1.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
174 /* Offset 0x10: IP-PRI Mapping Register 0
175 * Offset 0x11: IP-PRI Mapping Register 1
176 * Offset 0x12: IP-PRI Mapping Register 2
177 * Offset 0x13: IP-PRI Mapping Register 3
178 * Offset 0x14: IP-PRI Mapping Register 4
179 * Offset 0x15: IP-PRI Mapping Register 5
180 * Offset 0x16: IP-PRI Mapping Register 6
181 * Offset 0x17: IP-PRI Mapping Register 7
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| /linux/tools/testing/selftests/drivers/net/mlxsw/ |
| H A D | egress_vid_classification.sh | 2 # SPDX-License-Identifier: GPL-2.0
5 # configuration does not impact switch behavior. Verify that {RIF, Port}->VID
6 # mapping is added correctly for existing {Port, VID}->FID mapping and that
7 # {RIF, Port}->VID mapping is added correctly for new {Port, VID}->FID mapping.
9 # +-------------------+ +--------------------+
16 # +----------------|--+ +--|-----------------+
18 # +----------------|-------------------------|-----------------+
21 # | +--------------|-------------------------|---------------+ |
26 # | +--------------------------------------------------------+ |
32 # +---------------|--------------------------------------------+
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| /linux/arch/alpha/kernel/ |
| H A D | smc37c669.c | 60 * er 28-Jan-1997 Initial Entry
69 ** The mask acts as a flag used in mapping actual ISA IRQs (0 - 15)
70 ** to device IRQs (A - H).
83 ** The mask acts as a flag used in mapping actual ISA DMA
84 ** channels to device DMA channels (A - C).
218 ** CR00 - default value 0x28
221 ** 0x - 30ua pull-ups on nIDEEN, nHDCS0, NHDCS1
222 ** 11 - IRQ_H available as IRQ output,
224 ** 10 - nIDEEN, nHDCS0, nHDCS1 used to control IDE
247 ** CR01 - default value 0x9C
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| /linux/include/asm-generic/ |
| H A D | iomap.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
9 * These are the "generic" interfaces for doing new-style
10 * memory-mapped or PIO accesses. Architectures may do
11 * their own arch-optimized versions, these just act as
12 * wrappers around the old-style IO register access functions:
21 * encoded in the hardware mapping set up by the mapping functions
57 * They do _not_ update the port address. If you
62 extern void ioread8_rep(const void __iomem *port, void *buf, unsigned long count);
63 extern void ioread16_rep(const void __iomem *port, void *buf, unsigned long count);
64 extern void ioread32_rep(const void __iomem *port, void *buf, unsigned long count);
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| H A D | pci_iomap.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Generic I/O port emulation.
12 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
22 /* Create a virtual mapping cookie for a port on a given PCI device.
26 extern void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port,
29 #define __pci_ioport_map(dev, port, nr) NULL argument
31 #define __pci_ioport_map(dev, port, nr) ioport_map((port), (nr)) argument
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| /linux/Documentation/nvme/ |
| H A D | nvme-pci-endpoint-target.rst | 1 .. SPDX-License-Identifier: GPL-2.0
19 subsystem using a port. The port transfer type must be configured to be
47 segments representing the mapping of the command data buffer on the host.
57 -----------------------
65 mapping of a queue PCI address range to the local CPU address space.
78 ------------------
89 Minimum number of PCI Address Mapping Windows Required
90 ------------------------------------------------------
92 Most PCI endpoint controllers provide a limited number of mapping windows for
93 mapping a PCI address range to local CPU memory addresses. The NVMe PCI
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| /linux/drivers/net/ethernet/sunplus/ |
| H A D | spl2sw_int.c | 1 // SPDX-License-Identifier: GPL-2.0
30 int port; in spl2sw_rx_poll() local
34 /* Process high-priority queue and then low-priority queue. */ in spl2sw_rx_poll()
36 rx_pos = comm->rx_pos[queue]; in spl2sw_rx_poll()
37 rx_count = comm->rx_desc_num[queue]; in spl2sw_rx_poll()
40 sinfo = comm->rx_skb_info[queue] + rx_pos; in spl2sw_rx_poll()
41 desc = comm->rx_desc[queue] + rx_pos; in spl2sw_rx_poll()
42 cmd = desc->cmd1; in spl2sw_rx_poll()
47 port = FIELD_GET(RXD_PKT_SP, cmd); in spl2sw_rx_poll()
48 if (port < MAX_NETDEV_NUM && comm->ndev[port]) in spl2sw_rx_poll()
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| /linux/Documentation/core-api/ |
| H A D | cachetlb.rst | 25 virtual-->physical address translations obtained from the software
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
67 The interface is provided in hopes that the port can find
78 address space is available via vma->vm_mm. Also, one may
79 test (vma->vm_flags & VM_EXEC) to see if this region is
81 split-tlb type setups).
84 page table modification for address space 'vma->vm_mm' for
87 'vma->vm_mm' for virtual address 'addr'.
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| /linux/net/mptcp/ |
| H A D | mib.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 MPTCP_MIB_MPCAPABLEPASSIVEFALLBACK,/* Server-side fallback during 3-way handshake */
12 MPTCP_MIB_MPCAPABLEACTIVEFALLBACK, /* Client-side fallback during 3-way handshake */
13 MPTCP_MIB_MPCAPABLEACTIVEDROP, /* Client-side fallback due to a MPC drop */
14 MPTCP_MIB_MPCAPABLEACTIVEDISABLED, /* Client-side disabled due to past issues */
15 MPTCP_MIB_MPCAPABLEENDPATTEMPT, /* Prohibited MPC to port-based endp */
17 MPTCP_MIB_RETRANSSEGS, /* Segments retransmitted at the MPTCP-level */
31 MPTCP_MIB_DSSNOMATCH, /* Received a new mapping that did not match the previous one */
34 MPTCP_MIB_INFINITEMAPTX, /* Sent an infinite mapping */
35 MPTCP_MIB_INFINITEMAPRX, /* Received an infinite mapping */
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| /linux/tools/testing/selftests/drivers/net/hw/ |
| H A D | devlink_rate_tc_bw.py | 2 # SPDX-License-Identifier: GPL-2.0
8 This test suite verifies the functionality of devlink-rate traffic class (TC)
11 that TC mapping works as expected.
14 ----------------
15 - Creates 1 VF
16 - Establishes a bridge connecting the VF representor and the uplink representor
17 - Sets up 2 VLAN interfaces on the VF with different VLAN IDs (101, 102)
18 - Configures different traffic classes (TC3 and TC4) for each VLAN
21 ----------
23 - Verifies that without TC mapping, bandwidth is NOT distributed according to
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| /linux/Documentation/devicetree/bindings/display/panel/ |
| H A D | sgd,gktw70sdae4se.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
24 - compatible
29 - const: sgd,gktw70sdae4se
30 - const: panel-lvds
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| H A D | advantech,idk-1110wr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/advantech,idk-1110wr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Advantech IDK-1110WR 10.1" WSVGA LVDS Display Panel
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
21 const: advantech,idk-1110wr
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| H A D | mitsubishi,aa121td01.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/display/lvds.yaml#
24 - compatible
29 - const: mitsubishi,aa121td01
30 - const: panel-lvds
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| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | cpus.txt | 13 - fsl,eref-*
19 by the Power ISA. For these EREF-specific categories, the existence of
20 a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
24 - fsl,portid-mapping
27 Definition: The Coherency Subdomain ID Port Mapping Registers and
28 Snoop ID Port Mapping registers, which are part of the CoreNet
30 ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | cavium-pip.txt | 10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
29 - #size-cells: Must be <0>.
31 Properties for PIP port which is a child the PIP interface:
32 - compatible: "cavium,octeon-3860-pip-port"
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