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Searched full:pmucru (Results 1 – 25 of 31) sorted by relevance

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/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi233 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
247 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
261 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
276 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
287 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
298 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
309 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
320 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
331 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
342 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,px30-cru.yaml34 - rockchip,px30-pmucru
48 - description: Clock for both PMUCRU and CRU
49 - description: Clock for CRU (sourced from PMUCRU)
101 pmucru: clock-controller@ff2bc000 {
102 compatible = "rockchip,px30-pmucru";
114 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
H A Drockchip,rk3568-cru.yaml26 - rockchip,rk3568-pmucru
61 pmucru: clock-controller@fdd00000 {
62 compatible = "rockchip,rk3568-pmucru";
H A Drockchip,rk3399-cru.yaml36 - rockchip,rk3399-pmucru
71 pmucru: clock-controller@ff750000 {
72 compatible = "rockchip,rk3399-pmucru";
H A Drockchip,rv1126-cru.yaml22 - rockchip,rv1126-pmucru
/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x-base.dtsi372 pmucru: clock-controller@fdd00000 { label
373 compatible = "rockchip,rk3568-pmucru";
386 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
388 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
396 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
409 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
422 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
433 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
444 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
455 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
[all …]
H A Drk3566-powkiddy-rk2023.dts16 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-powkiddy-rgb30.dts16 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-powkiddy-rgb10max3.dts20 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
21 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3399-base.dtsi1318 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1331 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1344 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1346 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1359 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1361 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1374 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1376 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1392 clocks = <&pmucru PCLK_RKPWM_PMU>;
1402 clocks = <&pmucru PCLK_RKPWM_PMU>;
[all …]
H A Drk3568.dtsi142 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
346 clocks = <&pmucru CLK_PCIEPHY0_REF>,
350 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
H A Drk3566-anbernic-rg353x.dtsi81 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
82 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-box-demo.dts73 clocks = <&pmucru CLK_RTC_32K>;
451 clocks = <&pmucru CLK_RTC_32K>;
469 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Dpx30.dtsi377 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
832 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
849 pmucru: clock-controller@ff2bc000 { label
850 compatible = "rockchip,px30-pmucru";
859 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU>;
876 clocks = <&pmucru SCLK_USBPHY_REF>;
906 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
1397 clocks = <&pmucru PCLK_GPIO0_PMU>;
H A Drk3566-radxa-zero-3.dtsi517 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-orangepi-3b.dtsi665 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-odroid-m1s.dts650 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-anbernic-rgxx3.dtsi706 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-lckfb-tspi.dts712 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-odroid-m1.dts728 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-rock-3b.dts768 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-naneng-combphy.yaml133 clocks = <&pmucru CLK_PCIEPHY0_REF>,
137 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
H A Drockchip,px30-dsi-dphy.yaml65 clocks = <&pmucru 13>, <&cru 12>;
/linux/include/dt-bindings/clock/
H A Drk3568-cru.h10 /* pmucru-clocks indices */
12 /* pmucru plls */
16 /* pmucru clocks */
H A Drockchip,rv1126-cru.h10 /* pmucru-clocks indices */

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