| /freebsd/sys/contrib/device-tree/Bindings/mfd/ | 
| H A D | samsung,s5m8767.yaml | 14   Management IC (PMIC). 21     const: samsung,s5m8767-pmic 39   s5m8767,pmic-buck2-dvs-voltage: 47   s5m8767,pmic-buck3-dvs-voltage: 55   s5m8767,pmic-buck4-dvs-voltage: 63   s5m8767,pmic-buck-ds-gpios: 70   s5m8767,pmic-buck2-uses-gpio-dvs: 74   s5m8767,pmic-buck3-uses-gpio-dvs: 78   s5m8767,pmic-buck4-uses-gpio-dvs: 82   s5m8767,pmic-buck-default-dvs-idx: [all …] 
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| H A D | max8998.txt | 8 PMIC sub-block 11 The PMIC sub-block contains a number of voltage and current regulators, 20 - reg: Specifies the i2c slave address of the pmic block. It should be 0x66. 26 - max8998,pmic-buck1-dvs-gpios: GPIO specifiers for two host gpios used 29 - max8998,pmic-buck2-dvs-gpio: GPIO specifier for host gpio used 32 - max8998,pmic-buck1-default-dvs-idx: Default voltage setting selected from 36 - max8998,pmic-buck2-default-dvs-idx: Default voltage setting selected from 40 - max8998,pmic-buck-voltage-lock: If present, disallows changing of 43 Additional properties required if max8998,pmic-buck1-dvs-gpios is defined: 44 - max8998,pmic-buck1-dvs-voltage: An array of 4 voltage values in microvolts [all …] 
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| H A D | hisilicon,hi655x.txt | 1 Hisilicon Hi655x Power Management Integrated Circuit (PMIC) 3 The hardware layout for access PMIC Hi655x from AP SoC Hi6220. 4 Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. 15 - compatible:           Should be "hisilicon,hi655x-pmic". 16 - reg:                  Base address of PMIC on Hi6220 SoC. 18 - pmic-gpios:           The GPIO used by PMIC IRQ. 26 	pmic: pmic@f8000000 { 27 		compatible = "hisilicon,hi655x-pmic"; 31 		pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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| H A D | samsung,s2mps11.yaml | 14   Management IC (PMIC). 23       - samsung,s2mps11-pmic 24       - samsung,s2mps13-pmic 25       - samsung,s2mps14-pmic 26       - samsung,s2mps15-pmic 27       - samsung,s2mpu02-pmic 47       Indicates that ACOKB pin of S2MPS11 PMIC is connected to the ground so 48       the PMIC must manually set PWRHOLD bit in CTRL1 register to turn off the 55       Indicates that WRSTBI pin of PMIC is pulled down. When the system is 74             const: samsung,s2mps11-pmic [all …] 
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| H A D | samsung,sec-core.txt | 24 	- "samsung,s2mpa01-pmic", 25 	- "samsung,s2mps11-pmic", 26 	- "samsung,s2mps13-pmic", 27 	- "samsung,s2mps14-pmic", 28 	- "samsung,s2mps15-pmic", 29 	- "samsung,s2mpu02-pmic", 30 	- "samsung,s5m8767-pmic". 31  - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. 35  - samsung,s2mps11-wrstbi-ground: Indicates that WRSTBI pin of PMIC is pulled 38  - samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is [all …] 
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| H A D | mt6397.txt | 14 called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap. 22 	"mediatek,mt6323" for PMIC MT6323 23 	"mediatek,mt6331" for PMIC MT6331 and MT6332 24 	"mediatek,mt6357" for PMIC MT6357 25 	"mediatek,mt6358" for PMIC MT6358 26 	"mediatek,mt6359" for PMIC MT6359 27 	"mediatek,mt6366", "mediatek,mt6358" for PMIC MT6366 28 	"mediatek,mt6397" for PMIC MT6397 64 	see ../input/mtk-pmic-keys.txt 82 		pmic { [all...] | 
| /freebsd/sys/contrib/device-tree/Bindings/regulator/ | 
| H A D | maxim,max8997.yaml | 22     const: maxim,max8997-pmic 33   max8997,pmic-buck1-dvs-voltage: 40       If none of max8997,pmic-buck[1/2/5]-uses-gpio-dvs optional property is 41       specified, the max8997,pmic-buck[1/2/5]-dvs-voltage property should 45   max8997,pmic-buck2-dvs-voltage: 52       If none of max8997,pmic-buck[1/2/5]-uses-gpio-dvs optional property is 53       specified, the max8997,pmic-buck[1/2/5]-dvs-voltage property should 57   max8997,pmic-buck5-dvs-voltage: 64       If none of max8997,pmic-buck[1/2/5]-uses-gpio-dvs optional property is 65       specified, the max8997,pmic-buck[1/2/5]-dvs-voltage property should [all …] 
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| H A D | max8997-regulator.txt | 7 describes the bindings for 'pmic' sub-block of max8997. 10 - compatible: Should be "maxim,max8997-pmic". 11 - reg: Specifies the i2c slave address of the pmic block. It should be 0x66. 13 - max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV) 17 - max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV) 21 - max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV) 25 [1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional 26     property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage' 30     If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional 32     'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified. [all …] 
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| H A D | samsung,s5m8767.txt | 16  - s5m8767,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV) 20  - s5m8767,pmic-buck3-dvs-voltage: A set of 8 voltage values in micro-volt (uV) 24  - s5m8767,pmic-buck4-dvs-voltage: A set of 8 voltage values in micro-volt (uV) 28  - s5m8767,pmic-buck-ds-gpios: GPIO specifiers for three host gpio's used 31  [1] If none of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional 32      property is specified, the 's5m8767,pmic-buck[2/3/4]-dvs-voltage' 36      If either of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional 38      's5m8767,pmic-buck[2/3/4]-dvs-voltage' should be specified. 41  - s5m8767,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs. 42  - s5m8767,pmic-buck3-uses-gpio-dvs: 'buck3' can be controlled by gpio dvs. [all …] 
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| H A D | palmas-pmic.txt | 12   ti,twl6035-pmic 13   ti,twl6036-pmic 14   ti,twl6037-pmic 15   ti,tps65913-pmic 16   ti,tps65914-pmic 17   ti,tps65917-pmic 18   ti,tps659038-pmic 20   ti,palmas-pmic 35 	       For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP, 48 	       ti,mode-sleep - mode to adopt in pmic sleep 0 - off, 1 - auto, [all …] 
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| H A D | rohm,bd71815-regulator.yaml | 14   see Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml. 16   The regulator controller is represented as a sub-node of the PMIC node 56           PMIC "RUN" state voltage in uV when PMIC HW states are used. See 68           when PMIC transitions to SNVS.SNVS voltage depends on the previous 69           state (from which the PMIC transitioned to SNVS). 76           PMIC "SUSPEND" state voltage in uV when PMIC HW states are used. See 85           PMIC "LPSR" state voltage in uV when PMIC HW states are used. See
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| H A D | qcom,rpmh-regulator.txt | 3 rpmh-regulator devices support PMIC regulator management via the Voltage 10 enable state of any PMIC peripheral.  It is used for clock buffers, low-voltage 18 level describes the PMIC containing the regulators and must reside within an 19 RPMh device node.  The second level describes each regulator within the PMIC 23 The names used for regulator nodes must match those supported by a given PMIC. 38 First Level Nodes - PMIC 60 - qcom,pmic-id 64 		    this PMIC.  Typical values: "a", "b", "c", "d", "e", "f". 73 		    regulators for this PMIC. 101 		    regulators for this PMIC. [all …] 
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| /freebsd/sys/contrib/device-tree/Bindings/soc/qcom/ | 
| H A D | qcom,pmic-glink.yaml | 4 $id: http://devicetree.org/schemas/soc/qcom/qcom,pmic-glink.yaml# 7 title: Qualcomm PMIC GLINK firmware interface for battery management, USB 14   The PMIC GLINK service, running on a coprocessor on some modern Qualcomm 26               - qcom,qcm6490-pmic-glink 27               - qcom,sc8180x-pmic-glink 28               - qcom,sc8280xp-pmic-glink 29               - qcom,sm8350-pmic-glink 30               - qcom,sm8450-pmic-glink 31               - qcom,sm8550-pmic-glink 32           - const: qcom,pmic-glink [all …] 
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| /freebsd/sys/contrib/device-tree/Bindings/rtc/ | 
| H A D | rtc-mt6397.txt | 1 Device-Tree bindings for MediaTek PMIC based RTC 3 MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works 5 with PMIC wrapper bus which is a common resource shared with the other 6 functions found on the same PMIC. 8 For MediaTek PMIC MFD bindings, see: 11 For MediaTek PMIC wrapper bus bindings, see: 16        "mediatek,mt6323-rtc": for MT6323 PMIC 17        "mediatek,mt6358-rtc": for MT6358 PMIC 18        "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC 19        "mediatek,mt6397-rtc": for MT6397 PMIC [all …] 
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ | 
| H A D | x1e80100-pmics.dtsi | 197 	pmk8550: pmic@0 { 198 		compatible = "qcom,pm8550", "qcom,spmi-pmic"; 263 	pm8550: pmic@1 { 264 		compatible = "qcom,pm8550", "qcom,spmi-pmic"; 301 	pm8550ve_2: pmic@2 { 302 		compatible = "qcom,pm8550", "qcom,spmi-pmic"; 326 	pmc8380_3: pmic@3 { 327 		compatible = "qcom,pmc8380", "qcom,spmi-pmic"; 350 	pmc8380_4: pmic@4 { 351 		compatible = "qcom,pmc8380", "qcom,spmi-pmic"; [all …] 
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| H A D | sc8180x-pmics.dtsi | 69 	pmc8180_0: pmic@0 { 70 		compatible = "qcom,pm8150", "qcom,spmi-pmic"; 153 	pmic@1 { 154 		compatible = "qcom,pmc8180", "qcom,spmi-pmic"; 160 	pmic@2 { 161 		compatible = "qcom,smb2351", "qcom,spmi-pmic"; 194 	pmic@6 { 195 		compatible = "qcom,pm8150c", "qcom,spmi-pmic"; 201 	pmc8180_2: pmic@8 { 202 		compatible = "qcom,pm8150", "qcom,spmi-pmic"; [all …] 
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| H A D | pm8450a.dtsi | 10 	pm8450a: pmic@0 { 11 		compatible = "qcom,pm8150", "qcom,spmi-pmic"; 27 	pm8450c: pmic@4 { 28 		compatible = "qcom,pm8150", "qcom,spmi-pmic"; 44 	pm8450e: pmic@8 { 45 		compatible = "qcom,pm8150", "qcom,spmi-pmic"; 61 	pm8450g: pmic@c { 62 		compatible = "qcom,pm8150", "qcom,spmi-pmic";
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| H A D | sa8540p-pmics.dtsi | 11 	pmm8540a: pmic@0 { 12 		compatible = "qcom,pm8150", "qcom,spmi-pmic"; 36 	pmm8540c: pmic@4 { 37 		compatible = "qcom,pm8150", "qcom,spmi-pmic"; 62 	pmm8540e: pmic@8 { 63 		compatible = "qcom,pm8150", "qcom,spmi-pmic"; 79 	pmm8540g: pmic@c { 80 		compatible = "qcom,pm8150", "qcom,spmi-pmic";
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| /freebsd/sys/contrib/device-tree/Bindings/spmi/ | 
| H A D | qcom,spmi-pmic-arb.txt | 1 Qualcomm SPMI Controller (PMIC Arbiter) 3 The SPMI PMIC Arbiter is found on Snapdragon chipsets.  It is an SPMI 7 The PMIC Arbiter can also act as an interrupt controller, providing interrupts 17 - compatible : should be "qcom,spmi-pmic-arb". 22    Registers used only for V2 PMIC Arbiter: 26 - reg : address + size pairs describing the PMIC arb register sets; order must 31 - qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5) 32 - interrupts : interrupt list for the PMIC Arb controller, must contain a 36      "periph_irq" - summary interrupt for PMIC peripherals 37 - interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller [all …] 
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| H A D | hisilicon,hisi-spmi-controller.yaml | 16   The PMIC part is provided by 17   Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml. 48       PMIC properties, which are specific to the used SPMI PMIC device(s). 51       Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml 66         pmic@0 { 68             /* pmic properties */
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| H A D | qcom,spmi-pmic-arb.yaml | 4 $id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml# 7 title: Qualcomm SPMI Controller (PMIC Arbiter) 13   The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI 17   The PMIC Arbiter can also act as an interrupt controller, providing interrupts 25     const: qcom,spmi-pmic-arb 86       which of the PMIC Arb provided channels to use for accesses 93       SPMI bus instance. only applicable to PMIC arbiter version 7 and beyond. 108         compatible = "qcom,spmi-pmic-arb";
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| /freebsd/sys/contrib/device-tree/Bindings/soc/mediatek/ | 
| H A D | pwrap.txt | 1 MediaTek PMIC Wrapper Driver 3 This document describes the binding for the MediaTek PMIC wrapper. 5 On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface 6 is not directly visible to the CPU, but only through the PMIC wrapper 7 inside the SoC. The communication between the SoC and the PMIC can 13 on MT8135 the pins of some SoC internal peripherals can be on the PMIC. 52 - pmic: Using either MediaTek PMIC MFD as the child device of pwrap 72 		pmic {
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| H A D | mediatek,pwrap.yaml | 7 title: Mediatek PMIC Wrapper 14   On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface 15   is not directly visible to the CPU, but only through the PMIC wrapper 16   inside the SoC. The communication between the SoC and the PMIC can 22   On MT8135 the pins of some SoC internal peripherals can be on the PMIC. 61       - description: PMIC wrapper registers 92       - description: PMIC wrapper reset 101   pmic:
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ | 
| H A D | qcom,pmic-mpp.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml# 7 title: Qualcomm PMIC Multi-Purpose Pin (MPP) block 14   PMIC's from Qualcomm. 76       - $ref: "#/$defs/qcom-pmic-mpp-state" 79             $ref: "#/$defs/qcom-pmic-mpp-state" 83   qcom-pmic-mpp-state: 122           <dt-binding/pinctrl/qcom,pmic-mpp.h> PMIC_MPP_AOUT_LVL_* 143           <dt-bindings/pinctrl/qcom,pmic-mpp.h> PMIC_MPP_AMUX_ROUTE_CH5, 160     #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> 162     pmic {
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| /freebsd/sys/contrib/device-tree/Bindings/leds/ | 
| H A D | leds-mt6323.txt | 1 Device Tree Bindings for LED support on MT6323 PMIC 3 MT6323 LED controller is subfunction provided by MT6323 PMIC, so the LED 5 PMIC controller that is being defined as one kind of Muti-Function Device (MFD) 6 using shared bus called PMIC wrapper for each subfunction to access remote 7 MT6323 PMIC hardware. 11 For MediaTek PMIC wrapper bindings see: 36 	mt6323: pmic {
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