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Searched full:pllclk (Results 1 – 11 of 11) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsophgo,sg2042-clkgen.yaml52 clocks = <&pllclk 0>,
53 <&pllclk 1>,
54 <&pllclk 2>,
55 <&pllclk 3>;
H A Drenesas,h8s2678-pll-clock.txt18 pllclk: pllclk {
/freebsd/sys/contrib/device-tree/src/h8300/
H A Dh8s_sim.dts24 pllclk: pllclk { label
32 clocks = <&pllclk>;
H A Dedosk2674.dts25 pllclk: pllclk { label
33 clocks = <&pllclk>;
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Drenesas,dsi.yaml62 - const: pllclk
156 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dsg2042.dtsi168 pllclk: clock-controller@70300100c0 { label
187 clocks = <&pllclk MPLL_CLK>,
188 <&pllclk FPLL_CLK>,
189 <&pllclk DPLL0_CLK>,
190 <&pllclk DPLL1_CLK>;
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dmicrochip,pic32-clock.h17 #define PLLCLK 6 macro
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi886 <&pllclk JH7110_PLLCLK_PLL0_OUT>,
887 <&pllclk JH7110_PLLCLK_PLL1_OUT>,
888 <&pllclk JH7110_PLLCLK_PLL2_OUT>;
903 pllclk: clock-controller { label
H A Djh7110-common.dtsi368 <&pllclk JH7110_PLLCLK_PLL0_OUT>;
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr9a07g044.dtsi789 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
H A Dr9a07g054.dtsi794 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";