| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | allwinner,sun4i-a10-mod1-clk.yaml | 44 #include <dt-bindings/clock/sun4i-a10-pll2.h>
50 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
51 <&pll2 SUN4I_A10_PLL2_4X>,
52 <&pll2 SUN4I_A10_PLL2_2X>,
53 <&pll2 SUN4I_A10_PLL2_1X>;
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| H A D | renesas,r8a73a4-cpg-clocks.txt | 17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
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| H A D | renesas,sh73a0-cpg-clocks.txt | 19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
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| H A D | ti,cdce925.txt | 30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
49 PLL2 {
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| H A D | renesas,cpg-clocks.yaml | 80 - const: pll2
206 - const: pll2
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| H A D | prima2-clock.txt | 18 pll2 3
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| H A D | imx28-clock.yaml | 22 pll2 3
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| H A D | renesas,cpg-div6-clock.yaml | 60 clock-output-names = "main", "pll0", "pll1", "pll2",
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| H A D | st,nomadik.txt | 30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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| H A D | ti,cdce925.yaml | 98 PLL2 {
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| H A D | ti,lmk04832.yaml | 40 - description: PLL2 reference clock.
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| /freebsd/sys/arm/freescale/vybrid/ |
| H A D | vf_anadig.c | 57 #define ANADIG_PLL2_CTRL 0x030 /* PLL2 Control */
58 #define ANADIG_PLL2_SS 0x040 /* PLL2 Spread Spectrum */
59 #define ANADIG_PLL2_NUM 0x050 /* PLL2 Numerator */
60 #define ANADIG_PLL2_DENOM 0x060 /* PLL2 Denominator */
69 #define ANADIG_PLL2_PFD 0x100 /* PLL2 PFD */
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
242 pll2: pll2@0 { label
253 clocks = <&pll2>;
268 clocks = <&pll2>;
276 clocks = <&pll2>;
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | mediatek,mt8188-afe.yaml | 49 - description: audio pll2 clock
66 - description: audio pll2 divide 4
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| H A D | mt8195-afe-pcm.yaml | 45 - description: audio pll2 clock
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| /freebsd/sys/contrib/device-tree/Bindings/display/ti/ |
| H A D | ti,dra7-dss.txt | 24 'pll1', 'pll2_clkctrl', 'pll2'
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | qcom,mmcc-msm8960.h | 127 #define PLL2 118 macro
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| H A D | intel,lgm-clk.h | 30 /* PLL2 clocks */
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| H A D | stm32mp13-clks.h | 20 #define PLL2 7 macro
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| H A D | stm32mp1-clks.h | 184 #define PLL2 177 macro
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| H A D | imx8mq-clock.h | 49 /* AUDIO PLL2 */
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| H A D | tegra234-clock.h | 677 /** @brief Logical clk for setting GBE UPHY PLL2 TX_REF rate */
679 /** @brief Logical clk for setting GBE UPHY PLL2 XDIG rate */
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | dra74x.dtsi | 139 "pll2_clkctrl", "pll2";
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| /freebsd/sys/contrib/device-tree/src/arm64/sprd/ |
| H A D | ums512.dtsi | 297 pll2: clock-controller@0 { label
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| /freebsd/sys/contrib/device-tree/src/arm/renesas/ |
| H A D | sh73a0.dtsi | 651 clock-output-names = "main", "pll0", "pll1", "pll2",
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