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/linux/include/linux/clk/
H A Dat91_pmc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
26 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Susp…
38 #define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */
39 #define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */
40 #define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */
41 #define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */
43 #define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */
49 #define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
54 #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
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/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
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H A Dsilabs,si5341.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mike Looijmans <mike.looijmans@topic.nl>
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
25 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
33 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
42 - silabs,si5340
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/linux/drivers/media/pci/bt8xx/
H A Dbttv-cards.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 bttv-cards.c
6 this file has configuration information - card-specific stuff
9 Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
10 & Marcus Metzler (mocm@thp.uni-koeln.de)
11 (c) 1999-2001 Gerd Knorr <kraxel@goldbach.in-berlin.de>
31 #include <media/v4l2-common.h>
33 #include "bttv-audio-hook.h"
85 static unsigned int card[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
86 static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET }; variable
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/linux/Documentation/devicetree/bindings/spi/
H A Dbrcm,bcm63xx-hsspi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
15 Broadcom Broadband SoC supports High Speed SPI master controller since the
19 brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to
20 use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
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/linux/sound/soc/codecs/
H A Dadav80x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Lars-Peter Clausen <lars@metafoo.de>
46 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 argument
47 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) argument
48 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) argument
56 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) argument
59 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) argument
61 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) argument
62 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) argument
63 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) argument
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H A Dtlv320adc3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
8 // Copyright (C) 2014-2018, Ambarella, Inc.
15 #include <dt-bindings/sound/tlv320adc3xxx.h>
33 #include <sound/soc-dapm.h>
54 * PLL modes, to be used for clk_id for set_sysclk callback.
57 * table, which is intended to be the PLL based one if there is more than one.
59 * Setting the clock source using simple-card (clocks or
60 * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO.
63 #define ADC3XXX_PLL_ENABLE 1 /* Use PLL for clock generation */
64 #define ADC3XXX_PLL_BYPASS 2 /* Don't use PLL for clock generation */
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H A Dak4642.c1 // SPDX-License-Identifier: GPL-2.0
3 // ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
23 #include <linux/clk-provider.h>
85 #define MS (1 << 3) /* master/slave select */
102 #define LOPS (1 << 6) /* Stero Line-out Power Save Mode */
153 * min : 0xFE : -115.0 dB
156 static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
177 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in ak4642_lout_event()
280 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in ak4642_dai_startup()
281 struct snd_soc_component *component = dai->component; in ak4642_dai_startup()
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H A Dda7213.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 /* -54dB */
35 0x0, 0x11, TLV_DB_SCALE_ITEM(-5400, 0, 0),
36 /* -52.5dB to 15dB */
37 0x12, 0x3f, TLV_DB_SCALE_ITEM(-5250, 150, 0)
42 /* -78dB to 12dB */
43 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
52 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
53 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
54 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
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/linux/include/sound/
H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
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/linux/arch/arm/boot/dts/marvell/
H A Ddove-cubox.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
20 compatible = "gpio-leds";
21 pinctrl-0 = <&pmx_gpio_18>;
22 pinctrl-names = "default";
24 led-power {
27 default-state = "keep";
31 usb_power: regulator-1 {
32 compatible = "regulator-fixed";
33 regulator-name = "USB Power";
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/linux/drivers/i2c/busses/
H A Di2c-mlxbf.c1 // SPDX-License-Identifier: GPL-2.0
57 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
59 * memory-mapped region whose addresses are specified in either the DT or
64 * SMBus Master core clock frequency. Timing configurations are
66 * Master. Default value is set to 400MHz.
69 /* Reference clock for Bluefield - 156 MHz. */
72 /* Constant used to determine the PLL frequency. */
77 /* PLL registers. */
95 /* Master arbitration lost. */
111 /* Master busy bit reset. */
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/linux/drivers/staging/sm750fb/
H A Dddk750_chip.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 unsigned long input_freq; /* Input clock frequency to the PLL */
73 * Speed of master clock in MHz unit
75 * Others = the new master clock
97 unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
/linux/drivers/media/tuners/
H A Dtda18271.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 tda18271.h - header for the Philips / NXP TDA18271 silicon tuner
81 /* master / slave tuner: master uses main pll, slave uses cal pll */
/linux/drivers/clk/at91/
H A Dclk-master.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
46 static inline bool clk_master_ready(struct clk_master *master) in clk_master_ready() argument
48 unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY; in clk_master_ready()
51 regmap_read(master->regmap, AT91_PMC_SR, &status); in clk_master_ready()
58 struct clk_master *master = to_clk_master(hw); in clk_master_prepare() local
61 spin_lock_irqsave(master->lock, flags); in clk_master_prepare()
63 while (!clk_master_ready(master)) in clk_master_prepare()
66 spin_unlock_irqrestore(master->lock, flags); in clk_master_prepare()
73 struct clk_master *master = to_clk_master(hw); in clk_master_is_prepared() local
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H A Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
33 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
53 "atmel,sama5d2-clk-audio-pll-frac",
59 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
79 "atmel,sama5d2-clk-audio-pll-pad",
85 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
105 "atmel,sama5d2-clk-audio-pll-pmc",
161 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
162 name = gcknp->name; in of_sama5d2_clk_generated_setup()
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/linux/drivers/firmware/xilinx/
H A Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
28 #include <linux/firmware/xlnx-zynqmp.h>
29 #include <linux/firmware/xlnx-event-manager.h>
30 #include "zynqmp-debug.h"
37 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
39 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
54 * struct zynqmp_devinfo - Structure for Zynqmp device instance
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/linux/drivers/clk/bcm/
H A Dclk-iproc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
22 /* PLL that requires gating through ASIU */
25 /* PLL that has fractional part of the NDIV */
29 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
36 * Some PLLs require the PLL SW override bit to be set before changes can be
37 * applied to the PLL
43 * the PLL control register
54 * Some PLLs have an additional divide by 2 in master clock calculation;
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/linux/arch/sparc/include/asm/
H A Dfhc.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
45 #define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
46 #define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
51 #define FHC_CONTROL_XMSTR 0x00000100 /* 1=Causes this FHC to be XIR master*/
68 #define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
69 #define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */
/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2055.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define B2055_MASTER1 0x11 /* Master control 1 */
26 #define B2055_MASTER2 0x12 /* Master control 2 */
28 #define B2055_PD_PLLTS 0x14 /* PD PLL TS */
58 #define B2055_PLL_LFC1 0x32 /* PLL LF C1 */
59 #define B2055_PLL_CALVTH 0x33 /* PLL CAL VTH */
60 #define B2055_PLL_LFC2 0x34 /* PLL LF C2 */
61 #define B2055_PLL_REF 0x35 /* PLL reference */
62 #define B2055_PLL_LFR1 0x36 /* PLL LF R1 */
63 #define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */
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/linux/sound/soc/
H A Dsoc-dai.c1 // SPDX-License-Identifier: GPL-2.0
3 // soc-dai.c
10 #include <sound/soc-dai.h>
11 #include <sound/soc-link.h>
17 return snd_soc_ret(dai->dev, ret, in _soc_dai_ret()
18 "at %s() on %s\n", func, dai->name); in _soc_dai_ret()
25 #define soc_dai_mark_push(dai, substream, tgt) ((dai)->mark_##tgt = substream)
26 #define soc_dai_mark_pop(dai, tgt) ((dai)->mark
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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
27 #include <sound/omap-hdmi-audio.h>
42 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
55 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
56 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
97 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
100 if (PTR_ERR(reg) != -EPROBE_DEFER) in hdmi_init_regulator()
161 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
163 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
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H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #include <sound/omap-hdmi-audio.h>
46 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
59 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
60 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
116 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
173 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
175 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
182 r = dss_pll_enable(&hdmi.pll.pll); in hdmi_power_on_full()
184 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_legacy_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
40 struct drm_device *dev = crtc->dev; in radeon_overscan_setup()
41 struct radeon_device *rdev = dev->dev_private; in radeon_overscan_setup()
44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
52 struct drm_device *dev = crtc->dev; in radeon_legacy_rmx_mode_set()
53 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_rmx_mode_set()
55 int xres = mode->hdisplay; in radeon_legacy_rmx_mode_set()
56 int yres = mode->vdisplay; in radeon_legacy_rmx_mode_set()
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/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
46 /* Master Slice End Flag */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
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