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/linux/include/linux/clk/
H A Dat91_pmc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
26 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Susp…
38 #define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */
39 #define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */
40 #define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */
41 #define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */
43 #define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */
49 #define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
50 #define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */
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/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5341.txt6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
37 "silabs,si5344" - Si5344 A/B/C/D
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H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
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/linux/drivers/staging/sm750fb/
H A Dddk750_chip.c1 // SPDX-License-Identifier: GPL-2.0
58 struct pll_value pll; in set_chip_clock() local
66 * Set up PLL structure to hold the value to be set in clocks. in set_chip_clock()
68 pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in set_chip_clock()
69 pll.clock_type = MXCLK_PLL; in set_chip_clock()
73 * of the PLL structure. Sometimes, the chip cannot set in set_chip_clock()
78 sm750_calc_pll_value(frequency, &pll); in set_chip_clock()
80 /* Master Clock Control: MXCLK_PLL */ in set_chip_clock()
81 poke32(MXCLK_PLL_CTRL, sm750_format_pll_reg(&pll)); in set_chip_clock()
130 * This function set up the master clock (MCLK).
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H A Dddk750_chip.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 unsigned long input_freq; /* Input clock frequency to the PLL */
73 * Speed of master clock in MHz unit
75 * Others = the new master clock
97 unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
/linux/sound/soc/codecs/
H A Dda7210.c1 // SPDX-License-Identifier: GPL-2.0+
150 /* PLL bit fields */
217 u8 mode; /* 0 = slave, 1 = master */
220 /* PLL dividers table */
222 /* for MASTER mode, fs = 44.1Khz */
230 /* for MASTER mode, fs = 48Khz */
259 * min : 0x11 (-54.0 dB)
261 * reserved : 0x00 - 0x0F
267 /* -54 dB to +15 dB */
268 0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
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H A Dnau8822.c1 // SPDX-License-Identifier: GPL-2.0
3 // nau8822.c -- NAU8822 ALSA Soc Audio driver
8 // Co-author: John Hsu <kchsu0@nuvoton.com>
9 // Co-author: Seven Li <wtli@nuvoton.com>
185 struct soc_bytes_ext *params = (void *)kcontrol->private_value; in nau8822_eq_get()
190 val = (u16 *)ucontrol->value.bytes.data; in nau8822_eq_get()
192 for (i = 0; i < params->max / sizeof(u16); i++) { in nau8822_eq_get()
194 /* conversion of 16-bit integers between native CPU format in nau8822_eq_get()
206 * cut-off frequency, bandwidth control, and equalizer path.
217 struct soc_bytes_ext *params = (void *)kcontrol->private_value; in nau8822_eq_put()
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H A Dsrc4xxx.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright 2021-2022 Deqx Pty Ltd
17 bool master[2]; member
25 static const DECLARE_TLV_DB_SCALE(src_tlv, -12750, 50, 0);
133 {"SRC mclk source", "Master (MCLK)", "MCLK"},
134 {"SRC mclk source", "Master (RXCLKI)", "RXMCLKI"},
156 struct snd_soc_component *component = dai->component; in src4xxx_set_dai_fmt()
163 src4xxx->master[dai->id] = true; in src4xxx_set_dai_fmt()
167 src4xxx->master[dai->id] = false; in src4xxx_set_dai_fmt()
170 return -EINVAL; in src4xxx_set_dai_fmt()
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H A Dda9055.c1 // SPDX-License-Identifier: GPL-2.0-or-later
58 /* Input - Gain, Select and Filter Registers */
71 /* Output - Gain, Select and Filter Registers */
244 u8 mode; /* 0 = slave, 1 = master */
247 /* PLL divisor table */
249 /* for MASTER mode, fs = 44.1Khz and its harmonics */
259 /* for MASTER mode, fs = 48Khz and its harmonics */
288 0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
289 /* -54dB to 15dB */
290 0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
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H A Dadav80x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Lars-Peter Clausen <lars@metafoo.de>
46 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 argument
47 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) argument
48 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) argument
56 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) argument
59 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) argument
61 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) argument
62 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) argument
63 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) argument
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H A Dmax9860.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <sound/soc-dapm.h>
43 regcache_mark_dirty(max9860->regmap); in max9860_dvddio_event()
44 regcache_cache_only(max9860->regmap, true); in max9860_dvddio_event()
126 static const DECLARE_TLV_DB_SCALE(dva_tlv, -9100, 100, 1);
128 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
130 0, MAX9860_PAM_MAX - 1, TLV_DB_SCALE_ITEM(-2000, 2000, 1),
133 static const DECLARE_TLV_DB_SCALE(anth_tlv, -7600, 400, 1);
134 static const DECLARE_TLV_DB_SCALE(agcth_tlv, -1800, 100, 0);
181 SOC_SINGLE_TLV("Master Playback Volume", MAX9860_DACATTN,
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H A Dnau8810.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * nau8810.c -- NAU8810 ALSA Soc Audio driver
169 struct soc_bytes_ext *params = (void *)kcontrol->private_value; in nau8810_eq_get()
174 val = (u16 *)ucontrol->value.bytes.data; in nau8810_eq_get()
176 for (i = 0; i < params->max / sizeof(u16); i++) { in nau8810_eq_get()
177 regmap_read(nau8810->regmap, reg + i, &reg_val); in nau8810_eq_get()
178 /* conversion of 16-bit integers between native CPU format in nau8810_eq_get()
190 * cut-off frequency, bandwidth control, and equalizer path.
201 struct soc_bytes_ext *params = (void *)kcontrol->private_value; in nau8810_eq_put()
207 data = kmemdup(ucontrol->value.bytes.data, in nau8810_eq_put()
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H A Drk817_codec.c1 // SPDX-License-Identifier: GPL-2.0
32 * I don't have another implementation to compare from the Rockchip sources. Hard-coding for now.
45 if (rk817->mic_in_differential) { in rk817_init()
57 /* Set resistor value and charge pump current for PLL. */ in rk817_set_component_pll()
59 /* Set the PLL feedback clock divide value (values not documented). */ in rk817_set_component_pll()
61 /* Set the PLL pre-divide value (values not documented). */ in rk817_set_component_pll()
63 /* Set the PLL VCO output clock divide and PLL divided ratio of PLL High Clk (values not in rk817_set_component_pll()
73 * 0db~-95db, 0.375db/step, for example:
75 * 0xff: -95dB
78 static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, 0);
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/linux/drivers/media/pci/bt8xx/
H A Dbttv-cards.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 bttv-cards.c
6 this file has configuration information - card-specific stuff
9 Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
10 & Marcus Metzler (mocm@thp.uni-koeln.de)
11 (c) 1999-2001 Gerd Knorr <kraxel@goldbach.in-berlin.de>
31 #include <media/v4l2-common.h>
33 #include "bttv-audio-hook.h"
85 static unsigned int card[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET };
86 static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET }; variable
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/linux/Documentation/devicetree/bindings/spi/
H A Dbrcm,bcm63xx-hsspi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
15 Broadcom Broadband SoC supports High Speed SPI master controller since the
19 brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to
20 use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
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/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_14nm.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 * DSI PLL 14nm - clock diagram (eg: DSI0):
22 * +----+ | +----+
23 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
24 * +----+ | +----+
26 * | +----+ |
27 * o---| /2 |--o--|\
28 * | +----+ | \ +----+
29 * | | |--| n2 |-- dsi0pll
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/linux/include/sound/
H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
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/linux/arch/arm/boot/dts/marvell/
H A Ddove-cubox.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
20 compatible = "gpio-leds";
21 pinctrl-0 = <&pmx_gpio_18>;
22 pinctrl-names = "default";
24 led-power {
27 default-state = "keep";
31 usb_power: regulator-1 {
32 compatible = "regulator-fixed";
33 regulator-name = "USB Power";
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/linux/drivers/media/tuners/
H A Dtda18271.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 tda18271.h - header for the Philips / NXP TDA18271 silicon tuner
81 /* master / slave tuner: master uses main pll, slave uses cal pll */
/linux/drivers/clk/at91/
H A Dclk-master.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
46 static inline bool clk_master_ready(struct clk_master *master) in clk_master_ready() argument
48 unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY; in clk_master_ready()
51 regmap_read(master->regmap, AT91_PMC_SR, &status); in clk_master_ready()
58 struct clk_master *master = to_clk_master(hw); in clk_master_prepare() local
61 spin_lock_irqsave(master->lock, flags); in clk_master_prepare()
63 while (!clk_master_ready(master)) in clk_master_prepare()
66 spin_unlock_irqrestore(master->lock, flags); in clk_master_prepare()
73 struct clk_master *master = to_clk_master(hw); in clk_master_is_prepared() local
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += pmc.o sckc.o
7 obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
8 obj-y += clk-system.o clk-peripheral.o clk-programmable.o
10 obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll.o
11 obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
12 obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
13 obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
14 obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
15 obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
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/linux/drivers/clk/bcm/
H A Dclk-iproc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
17 #define bit_mask(width) ((1 << (width)) - 1)
22 /* PLL that requires gating through ASIU */
25 /* PLL that has fractional part of the NDIV */
29 * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
36 * Some PLLs require the PLL SW override bit to be set before changes can be
37 * applied to the PLL
43 * the PLL control register
54 * Some PLLs have an additional divide by 2 in master clock calculation;
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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
21 - items:
22 - enum:
23 - fsl,imx6ul-sai
24 - fsl,imx7d-sai
25 - const: fsl,imx6sx-sai
27 - items:
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/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
31 #include <sound/omap-hdmi-audio.h>
47 r = pm_runtime_get_sync(&hdmi->pdev->dev); in hdmi_runtime_get()
49 pm_runtime_put_noidle(&hdmi->pdev->dev); in hdmi_runtime_get()
61 r = pm_runtime_put_sync(&hdmi->pdev->dev); in hdmi_runtime_put()
62 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
68 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler()
91 v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_irq_handler()
94 hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); in hdmi_irq_handler()
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/linux/arch/sparc/include/asm/
H A Dfhc.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
45 #define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */
46 #define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */
51 #define FHC_CONTROL_XMSTR 0x00000100 /* 1=Causes this FHC to be XIR master*/
68 #define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */
69 #define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */

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