Lines Matching +full:pll +full:- +full:master
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
26 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Susp…
38 #define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */
39 #define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */
40 #define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */
41 #define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */
43 #define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */
49 #define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
50 #define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */
51 #define AT91_PMC_PLL_ACR_DEFAULT_PLLA UL(0x00020010) /* Default PLL ACR value for PLLA */
56 #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
57 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
59 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
61 #define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */
62 #define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */
63 #define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */
64 #define AT91_PMC_PLL_UPDT_ID_MSK (0xf) /* PLL ID mask */
71 #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
72 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
82 #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
87 #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
89 #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
90 #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
91 #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
93 #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */
103 #define AT91_PMC_MCKR 0x30 /* Master Clock Register */
104 #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
111 #define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */
120 #define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate locati…
128 #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
146 #define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */
188 #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
191 #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
201 #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
209 #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
212 #define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */
221 #define AT91_PMC_LPM BIT(20) /* Low-power Mode */
229 #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
240 #define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */