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/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-xe-hwmon5 Description: RW. Card reactive sustained (PL1) power limit in microwatts.
9 exceeds this limit. A read value of 0 means that the PL1
36 Description: RW. Card sustained power limit interval (Tau in PL1/Tau) in
45 Description: RW. Package reactive sustained (PL1) power limit in microwatts.
49 exceeds this limit. A read value of 0 means that the PL1
99 Description: RW. Package sustained power limit interval (Tau in PL1/Tau) in
162 PL2 is greater than PL1 and its time window is lesser
163 compared to PL1.
177 PL2 is greater than PL1 and its time window is lesser
178 compared to PL1.
H A Dsysfs-driver-intel-i915-hwmon13 Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts.
17 exceeds this limit. A read value of 0 means that the PL1
35 Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
H A Dsysfs-platform-asus-wmi143 Set the Package Power Target total of CPU: PL1 on Intel, SPL on AMD.
/linux/drivers/platform/x86/hp/
H A Dhp-wmi.c161 u8 pl1; member
1640 /* Note: HP_POWER_LIMIT_DEFAULT can be used to restore default PL1 and PL2 */
1641 static int victus_s_set_cpu_pl1_pl2(u8 pl1, u8 pl2) in victus_s_set_cpu_pl1_pl2() argument
1646 /* We need to know both PL1 and PL2 values in order to check them */ in victus_s_set_cpu_pl1_pl2()
1647 if (pl1 == HP_POWER_LIMIT_NO_CHANGE || pl2 == HP_POWER_LIMIT_NO_CHANGE) in victus_s_set_cpu_pl1_pl2()
1650 /* PL2 is not supposed to be lower than PL1 */ in victus_s_set_cpu_pl1_pl2()
1651 if (pl2 < pl1) in victus_s_set_cpu_pl1_pl2()
1654 power_limits.pl1 = pl1; in victus_s_set_cpu_pl1_pl2()
1843 pr_debug("Triggering CPU PL1/PL2 actualization\n"); in victus_s_powersource_event()
/linux/drivers/gpu/drm/xe/
H A Dxe_hwmon.c87 #define PWR_ATTR_TO_STR(attr) (((attr) == hwmon_power_max) ? "PL1" : "PL2")
136 /** @pl1_on_boot: power limit PL1 on boot */
282 * HW allows arbitrary PL1 limits to be set but silently clamps these values to
284 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
413 /* PL1 is rated max if supported. */ in xe_hwmon_power_rated_max_read()
624 /* PSYS PL1 */
628 /* PKG PL1 */
/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-bananapi-m2-plus-v1.2.dtsi22 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
H A Dsun8i-h2-plus-bananapi-m2-zero.dts71 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
H A Dsun8i-a23-a33.dtsi823 pins = "PL0", "PL1";
829 pins = "PL0", "PL1";
/linux/Documentation/arch/arm/
H A Dbooting.rst222 the HYP mode configuration in addition to the ordinary PL1 (privileged
224 hypervisor must be disabled, and PL1 access must be granted for all
/linux/drivers/gpu/drm/i915/
H A Di915_hwmon.c402 * HW allows arbitrary PL1 limits to be set but silently clamps these values to
404 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
414 /* Check if PL1 limit is disabled */ in hwm_power_max_read()
474 /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ in hwm_power_max_write()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra210-pinmux.yaml56 pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
/linux/arch/arm/kernel/
H A Dhead-nommu.S291 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
303 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
H A Dhyp-stub.S146 @ make CNTP_* and CNTPCT accessible from PL1
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6-beelink-gs1.dts285 * PL0 and PL1 are used for PMIC I2C
H A Dsun50i-h616.dtsi918 pins = "PL0", "PL1";
923 pins = "PL0", "PL1";
H A Dsun50i-h6.dtsi1007 pins = "PL0", "PL1";
1017 pins = "PL0", "PL1";
H A Dsun50i-a100.dtsi577 pins = "PL0", "PL1";
/linux/arch/parisc/kernel/
H A Dentry.S517 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
523 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
526 * which have _PAGE_READ zero (PL <= PL1). Thus, the kernel
607 * to type field and _PAGE_READ goes to top bit of PL1
/linux/drivers/media/i2c/
H A Dsaa6588.c117 /* bits 6+7 (PL0/PL1) */
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210-p2595.dtsi604 pl1 {
605 nvidia,pins = "pl1";
H A Dtegra210-p2571.dts615 pl1 {
616 nvidia,pins = "pl1";
H A Dtegra210-p2894.dtsi631 pl1 {
632 nvidia,pins = "pl1";
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra210.c267 PINCTRL_PIN(TEGRA_PIN_PL1, "PL1"),
1509 …PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, N,…
1532 DRV_PINGROUP(pl1, 0x9f8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_uc.c491 /* Disable a potentially low PL1 power limit to allow freq to be raised */ in __uc_init_hw()
/linux/Documentation/i2c/
H A Di2c-topology.rst173 [PL1]

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