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/linux/drivers/gpu/drm/udl/
H A Dudl_transfer.c29 static inline u16 pixel32_to_be16(const uint32_t pixel) in pixel32_to_be16() argument
31 return (((pixel >> 3) & 0x001f) | in pixel32_to_be16()
32 ((pixel >> 5) & 0x07e0) | in pixel32_to_be16()
33 ((pixel >> 8) & 0xf800)); in pixel32_to_be16()
36 static inline u16 get_pixel_val16(const uint8_t *pixel, int log_bpp) in get_pixel_val16() argument
40 pixel_val16 = *(const uint16_t *)pixel; in get_pixel_val16()
42 pixel_val16 = pixel32_to_be16(*(const uint32_t *)pixel); in get_pixel_val16()
65 * Rather than 256 pixel commands which are either rl or raw encoded,
70 * compression than 256 pixel raw or rle commands, with similar CPU consumpion.
81 const u8 *pixel = *pixel_start_ptr; in udl_compress_hline16() local
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pixel-link.yaml4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
15 camera module) and pixel consumers(imaging or displays).
16 It consists of two distinct functions, a pixel transfer function and a
17 control interface. Multiple pixel channels can exist per one control channel.
18 This binding documentation is only for pixel links whose pixel sources are
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
27 - fsl,imx8qm-dc-pixel-link
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H A Dfsl,imx8qxp-pixel-combiner.yaml4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
15 of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
16 either one screen, two screens, or virtual screens. The pixel combiner is
17 also responsible for generating some of the control signals for the pixel link
23 - fsl,imx8qm-pixel-combiner
24 - fsl,imx8qxp-pixel-combiner
47 description: Represents a display stream of pixel combiner.
92 pixel-combiner@56020000 {
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H A Dfsl,imx8qxp-pxl2dpi.yaml7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
14 interfaces the pixel link 36-bit data output and the DSI controller’s
16 used in LVDS mode, to remap the pixel color codings between those modules.
46 description: The PXL2DPI input port node from pixel link.
/linux/drivers/video/fbdev/core/
H A Dfb_draw.h21 * Create a pattern with the given pixel's color
26 pixel_to_pat( u32 bpp, u32 pixel) in pixel_to_pat() argument
30 return 0xfffffffffffffffful*pixel; in pixel_to_pat()
32 return 0x5555555555555555ul*pixel; in pixel_to_pat()
34 return 0x1111111111111111ul*pixel; in pixel_to_pat()
36 return 0x0101010101010101ul*pixel; in pixel_to_pat()
38 return 0x1001001001001001ul*pixel; in pixel_to_pat()
40 return 0x0001000100010001ul*pixel; in pixel_to_pat()
42 return 0x0001000001000001ul*pixel; in pixel_to_pat()
44 return 0x0000000100000001ul*pixel; in pixel_to_pat()
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/linux/drivers/gpu/drm/vkms/
H A Dvkms_formats.c13 * packed_pixels_offset() - Get the offset of the block containing the pixel at coordinates x/y
16 * @x: The x coordinate of the wanted pixel in the buffer
17 * @y: The y coordinate of the wanted pixel in the buffer
20 * @rem_x: The returned X coordinate of the requested pixel in the block
21 * @rem_y: The returned Y coordinate of the requested pixel in the block
23 * As some pixel formats store multiple pixels in a block (DRM_FORMAT_R* for example), some
25 * whole block, and the coordinate of the requested pixel inside this block.
30 * With this function, the caller just have to extract the correct pixel from the block.
41 * containing the pixel. in packed_pixels_offset()
56 * packed_pixels_addr() - Get the pointer to the block containing the pixel at the given
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/linux/include/uapi/linux/dvb/
H A Dosd.h41 * Sets all pixel to color 0
46 * Sets all pixel to color <col>
54 * opacity=0: pixel opacity 0% (only video pixel shows)
55 * opacity=1..254: pixel opacity as specified in header
56 * opacity=255: pixel opacity 100% (only OSD pixel shows)
64 * R,G,B, and a opacity value: 0->transparent, 1..254->mix, 255->pixel
68 * Sets transparency of mixed pixel (0..15)
73 * sets pixel <x>,<y> to color number <col>
77 /* returns color number of pixel <x>,<y>, or -1 */
81 * returns 0 on success, -1 on clipping all pixel (no pixel drawn)
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/linux/Documentation/gpu/amdgpu/display/
H A Ddisplay-manager.rst90 Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
99 pixel color values and, therefore, the resulted pixel color. For
102 - *fg.rgb*: Each of the RGB component values from the foreground's pixel.
103 - *fg.alpha*: Alpha component value from the foreground's pixel.
112 the alpha channel value of each pixel in a plane is ignored and only the plane
113 alpha affects the resulted pixel color values.
117 * **None**: Blend formula that ignores the pixel alpha.
119 * **Pre-multiplied**: Blend formula that assumes the pixel color values in a
122 * **Coverage**: Blend formula that assumes the pixel color values were not
125 and pre-multiplied is the default pixel blend mode, that means, when no blend
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H A Ddc-glossary.rst31 Bits Per Pixel
34 * PCLK: Pixel Clock
41 * PPLL: Pixel PLL
50 raw stream of pixels, clocked at pixel clock
95 Display Stream Compression (Reduce the amount of bits to represent pixel
96 count while at the same pixel clock)
/linux/drivers/media/i2c/ccs/
H A Dccs-data.h112 * struct ccs_pdaf_pix_loc_block_desc - PDAF pixel location block descriptor
122 * struct ccs_pdaf_pix_loc_block_desc_group - PDAF pixel location block
135 * struct ccs_pdaf_pix_loc_pixel_desc - PDAF pixel location block descriptor
136 * @pixel_type: Type of the pixel; CCS_DATA_PDAF_PIXEL_TYPE_*
147 * struct ccs_pdaf_pix_loc_pixel_desc_group - PDAF pixel location pixel
150 * @descs: PDAF pixel location pixel descriptors
158 * struct ccs_pdaf_pix_loc - PDAF pixel locations
159 * @main_offset_x: Start X coordinate of PDAF pixel blocks
160 * @main_offset_y: Start Y coordinate of PDAF pixel blocks
166 * @num_pixel_desc_grups: Number of pixel descriptor groups
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/linux/Documentation/userspace-api/
H A Ddma-buf-alloc-exchange.rst5 Exchanging pixel buffers
9 support for sharing pixel-buffer allocations between processes, devices, and
26 in one or more memory buffers. Has width and height in pixels, pixel
41 A piece of memory for storing (parts of) pixel data. Has stride and size
49 pixel:
54 pixel data:
56 of a pixel or an image. The data for one pixel may be spread over several
68 pixel format:
69 A description of how pixel data represents the pixel's color and alpha
73 A description of how pixel data is laid out in memory buffers.
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/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-core.h101 * @mbus_code: Media Bus pixel code, -1 if not applicable
108 * @depth: per plane driver's private 'number of bits per pixel'
217 * struct gsc_pix_max - image pixel size limits in various IP configurations
219 * @org_scaler_bypass_w: max pixel width when the scaler is disabled
220 * @org_scaler_bypass_h: max pixel height when the scaler is disabled
221 * @org_scaler_input_w: max pixel width when the scaler is enabled
222 * @org_scaler_input_h: max pixel height when the scaler is enabled
223 * @real_rot_dis_w: max pixel src cropped height with the rotator is off
224 * @real_rot_dis_h: max pixel src cropped width with the rotator is off
225 * @real_rot_en_w: max pixel src cropped width with the rotator is on
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/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-enum-framesizes.rst30 that contains an index and pixel format and receives a frame width
37 and height in pixels) that the device supports for the given pixel
40 The supported pixel formats can be obtained by using the
99 - Width of the frame [pixel].
102 - Height of the frame [pixel].
114 - Minimum frame width [pixel].
117 - Maximum frame width [pixel].
120 - Frame width step size [pixel].
123 - Minimum frame height [pixel].
126 - Maximum frame height [pixel].
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H A Dfourcc.rst3 Guidelines for Video4Linux pixel format 4CCs
8 the pixel format, compression and colour space. The interpretation of the
23 2nd character: pixel order
30 3rd character: uncompressed bits-per-pixel 0--9, A--
32 4th character: compressed bits-per-pixel 0--9, A--
/linux/Documentation/devicetree/bindings/media/
H A Dcdns,csi2rx.yaml14 lanes in input, and 4 different pixel streams in output.
31 - description: pixel Clock for Stream interface 0
32 - description: pixel Clock for Stream interface 1
33 - description: pixel Clock for Stream interface 2
34 - description: pixel Clock for Stream interface 3
49 - description: pixel reset for Stream interface 0
50 - description: pixel reset for Stream interface 1
51 - description: pixel reset for Stream interface 2
52 - description: pixel reset for Stream interface 3
/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
29 pixel link MSI bus controller and does not allow SCFW user to control it.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
52 - fsl,imx8qxp-display-pixel-link-msi-bus
53 - fsl,imx8qm-display-pixel-link-msi-bus
94 compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
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/linux/Documentation/devicetree/bindings/arm/
H A Dgoogle.yaml13 ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
16 Currently upstream this is devices using "gs101" SoC which is found in Pixel
17 6, Pixel 6 Pro and Pixel 6a.
26 - Marketing name ("Pixel 6")
37 - description: Google Pixel 6 / Oriole
/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-controller-main.yaml69 - pixel:: Display pixel clock.
110 Parents of "byte" and "pixel" for the given platform.
118 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
242 - const: pixel
261 - const: pixel
281 - const: pixel
301 - const: pixel
322 - const: pixel
341 - const: pixel
369 - const: pixel
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/linux/drivers/video/fbdev/
H A Dvalkyriefb.h102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
171 { 23, 37, 2 }, /* pixel clock = 25.14MHz for V=59.85Hz */
H A Dpxa3xx-regs.h72 #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) argument
96 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
99 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
118 #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
119 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
120 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
126 #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
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/linux/drivers/media/i2c/
H A Dccs-pll.h59 * @pix_clk_div: Pixel clock divider
61 * @pix_clk_freq_hz: Pixel clock frequency
84 * @bits_per_pixel: Bits per pixel on the output data bus (input)
94 * @pixel_rate_csi: Pixel rate on the output data bus (output)
95 * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
156 * @min_pix_clk_div: Minimum pixel clock divider
157 * @max_pix_clk_div: Maximum pixel clock divider
158 * @min_pix_clk_freq_hz: Minimum pixel clock frequency
159 * @max_pix_clk_freq_hz: Maximum pixel clock frequency
/linux/Documentation/userspace-api/media/dvb/
H A Dlegacy_dvb_osd.rst130 - | Sets all pixel to color 0.
139 - | Sets all pixel to color <color>.
153 | opacity=0: pixel opacity 0% (only video pixel shows)
154 | opacity=1..254: pixel opacity as specified in header
155 | opacity=255: pixel opacity 100% (only OSD pixel shows)
170 255->pixel
178 - | Sets transparency of mixed pixel (0..15).
187 - | Sets pixel <x>,<y> to color number <color>.
196 - | Returns color number of pixel <x>,<y>, or -1.
206 | Returns 0 on success, -1 on clipping all pixel (no pixel
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/linux/drivers/staging/media/atomisp/include/linux/
H A Datomisp_platform.h51 ATOMISP_INPUT_FORMAT_RAW_6, /* RAW data, 6 bits per pixel */
52 ATOMISP_INPUT_FORMAT_RAW_7, /* RAW data, 7 bits per pixel */
53 ATOMISP_INPUT_FORMAT_RAW_8, /* RAW data, 8 bits per pixel */
54 ATOMISP_INPUT_FORMAT_RAW_10, /* RAW data, 10 bits per pixel */
55 ATOMISP_INPUT_FORMAT_RAW_12, /* RAW data, 12 bits per pixel */
56 ATOMISP_INPUT_FORMAT_RAW_14, /* RAW data, 14 bits per pixel */
57 ATOMISP_INPUT_FORMAT_RAW_16, /* RAW data, 16 bits per pixel */
76 Pixel Sampling) */
78 Pixel Sampling) */
/linux/drivers/staging/fbtft/
H A Dfb_agm1264k-fl.c247 signed short pixel, signed short error) in iterate_diffusion_matrix() argument
264 /* pixel itself */ in iterate_diffusion_matrix()
265 *write_pos = pixel; in iterate_diffusion_matrix()
295 u16 pixel = vmem16[y * par->info->var.xres + x]; in write_vmem() local
296 u16 b = pixel & 0x1f; in write_vmem()
297 u16 g = (pixel & (0x3f << 5)) >> 5; in write_vmem()
298 u16 r = (pixel & (0x1f << (5 + 6))) >> (5 + 6); in write_vmem()
300 pixel = (299 * r + 587 * g + 114 * b) / 200; in write_vmem()
301 if (pixel > 255) in write_vmem()
302 pixel = 255; in write_vmem()
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/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-core.h83 * struct camif_fmt - pixel format description
88 * @depth: bits per pixel (total)
89 * @ybpp: number of luminance bytes per pixel
101 * struct camif_dma_offset - pixel offset information for DMA
102 * @initial: offset (in pixels) to first pixel
112 * @f_width: full pixel width
113 * @f_height: full pixel height
146 * @vp_pix_limits: pixel limits for the codec and preview paths
147 * @pix_limits: pixel limits for the camera input interface
199 * @out_fmt: pixel format at this video path output
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