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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pixel-link.yaml4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
15 camera module) and pixel consumers(imaging or displays).
16 It consists of two distinct functions, a pixel transfer function and a
17 control interface. Multiple pixel channels can exist per one control channel.
18 This binding documentation is only for pixel links whose pixel sources are
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
27 - fsl,imx8qm-dc-pixel-link
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H A Dfsl,imx8qxp-pixel-combiner.yaml4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
15 of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
16 either one screen, two screens, or virtual screens. The pixel combiner is
17 also responsible for generating some of the control signals for the pixel link
23 - fsl,imx8qm-pixel-combiner
24 - fsl,imx8qxp-pixel-combiner
47 description: Represents a display stream of pixel combiner.
92 pixel-combiner@56020000 {
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H A Dfsl,imx8qxp-pxl2dpi.yaml7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
14 interfaces the pixel link 36-bit data output and the DSI controller’s
16 used in LVDS mode, to remap the pixel color codings between those modules.
46 description: The PXL2DPI input port node from pixel link.
/linux/include/uapi/linux/dvb/
H A Dosd.h41 * Sets all pixel to color 0
46 * Sets all pixel to color <col>
54 * opacity=0: pixel opacity 0% (only video pixel shows)
55 * opacity=1..254: pixel opacity as specified in header
56 * opacity=255: pixel opacity 100% (only OSD pixel shows)
64 * R,G,B, and a opacity value: 0->transparent, 1..254->mix, 255->pixel
68 * Sets transparency of mixed pixel (0..15)
73 * sets pixel <x>,<y> to color number <col>
77 /* returns color number of pixel <x>,<y>, or -1 */
81 * returns 0 on success, -1 on clipping all pixel (no pixel drawn)
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/linux/Documentation/gpu/amdgpu/display/
H A Ddisplay-manager.rst90 Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
99 pixel color values and, therefore, the resulted pixel color. For
102 - *fg.rgb*: Each of the RGB component values from the foreground's pixel.
103 - *fg.alpha*: Alpha component value from the foreground's pixel.
112 the alpha channel value of each pixel in a plane is ignored and only the plane
113 alpha affects the resulted pixel color values.
117 * **None**: Blend formula that ignores the pixel alpha.
119 * **Pre-multiplied**: Blend formula that assumes the pixel color values in a
122 * **Coverage**: Blend formula that assumes the pixel color values were not
125 and pre-multiplied is the default pixel blend mode, that means, when no blend
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/linux/drivers/media/i2c/ccs/
H A Dccs-data.h112 * struct ccs_pdaf_pix_loc_block_desc - PDAF pixel location block descriptor
122 * struct ccs_pdaf_pix_loc_block_desc_group - PDAF pixel location block
135 * struct ccs_pdaf_pix_loc_pixel_desc - PDAF pixel location block descriptor
136 * @pixel_type: Type of the pixel; CCS_DATA_PDAF_PIXEL_TYPE_*
147 * struct ccs_pdaf_pix_loc_pixel_desc_group - PDAF pixel location pixel
150 * @descs: PDAF pixel location pixel descriptors
158 * struct ccs_pdaf_pix_loc - PDAF pixel locations
159 * @main_offset_x: Start X coordinate of PDAF pixel blocks
160 * @main_offset_y: Start Y coordinate of PDAF pixel blocks
166 * @num_pixel_desc_grups: Number of pixel descriptor groups
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/linux/Documentation/userspace-api/
H A Ddma-buf-alloc-exchange.rst5 Exchanging pixel buffers
9 support for sharing pixel-buffer allocations between processes, devices, and
26 in one or more memory buffers. Has width and height in pixels, pixel
41 A piece of memory for storing (parts of) pixel data. Has stride and size
49 pixel:
54 pixel data:
56 of a pixel or an image. The data for one pixel may be spread over several
68 pixel format:
69 A description of how pixel data represents the pixel's color and alpha
73 A description of how pixel data is laid out in memory buffers.
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/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-core.h101 * @mbus_code: Media Bus pixel code, -1 if not applicable
108 * @depth: per plane driver's private 'number of bits per pixel'
217 * struct gsc_pix_max - image pixel size limits in various IP configurations
219 * @org_scaler_bypass_w: max pixel width when the scaler is disabled
220 * @org_scaler_bypass_h: max pixel height when the scaler is disabled
221 * @org_scaler_input_w: max pixel width when the scaler is enabled
222 * @org_scaler_input_h: max pixel height when the scaler is enabled
223 * @real_rot_dis_w: max pixel src cropped height with the rotator is off
224 * @real_rot_dis_h: max pixel src cropped width with the rotator is off
225 * @real_rot_en_w: max pixel src cropped width with the rotator is on
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/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-enum-framesizes.rst30 that contains an index and pixel format and receives a frame width
37 and height in pixels) that the device supports for the given pixel
40 The supported pixel formats can be obtained by using the
99 - Width of the frame [pixel].
102 - Height of the frame [pixel].
114 - Minimum frame width [pixel].
117 - Maximum frame width [pixel].
120 - Frame width step size [pixel].
123 - Minimum frame height [pixel].
126 - Maximum frame height [pixel].
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H A Dfourcc.rst3 Guidelines for Video4Linux pixel format 4CCs
8 the pixel format, compression and colour space. The interpretation of the
23 2nd character: pixel order
30 3rd character: uncompressed bits-per-pixel 0--9, A--
32 4th character: compressed bits-per-pixel 0--9, A--
/linux/Documentation/devicetree/bindings/media/
H A Dcdns,csi2rx.yaml14 lanes in input, and 4 different pixel streams in output.
31 - description: pixel Clock for Stream interface 0
32 - description: pixel Clock for Stream interface 1
33 - description: pixel Clock for Stream interface 2
34 - description: pixel Clock for Stream interface 3
49 - description: pixel reset for Stream interface 0
50 - description: pixel reset for Stream interface 1
51 - description: pixel reset for Stream interface 2
52 - description: pixel reset for Stream interface 3
/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
29 pixel link MSI bus controller and does not allow SCFW user to control it.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
52 - fsl,imx8qxp-display-pixel-link-msi-bus
53 - fsl,imx8qm-display-pixel-link-msi-bus
94 compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
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/linux/Documentation/devicetree/bindings/arm/
H A Dgoogle.yaml13 ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
16 Currently upstream this is devices using "gs101" SoC which is found in Pixel
17 6, Pixel 6 Pro and Pixel 6a.
26 - Marketing name ("Pixel 6")
37 - description: Google Pixel 6 or 6 Pro (Oriole or Raven)
/linux/drivers/video/fbdev/
H A Dvalkyriefb.h102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
171 { 23, 37, 2 }, /* pixel clock = 25.14MHz for V=59.85Hz */
H A Dpxa3xx-regs.h72 #define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) argument
96 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
99 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
118 #define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
119 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
120 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
126 #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
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/linux/Documentation/userspace-api/media/dvb/
H A Dlegacy_dvb_osd.rst130 - | Sets all pixel to color 0.
139 - | Sets all pixel to color <color>.
153 | opacity=0: pixel opacity 0% (only video pixel shows)
154 | opacity=1..254: pixel opacity as specified in header
155 | opacity=255: pixel opacity 100% (only OSD pixel shows)
170 255->pixel
178 - | Sets transparency of mixed pixel (0..15).
187 - | Sets pixel <x>,<y> to color number <color>.
196 - | Returns color number of pixel <x>,<y>, or -1.
206 | Returns 0 on success, -1 on clipping all pixel (no pixel
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/linux/drivers/staging/fbtft/
H A Dfb_agm1264k-fl.c247 signed short pixel, signed short error) in iterate_diffusion_matrix() argument
264 /* pixel itself */ in iterate_diffusion_matrix()
265 *write_pos = pixel; in iterate_diffusion_matrix()
295 u16 pixel = vmem16[y * par->info->var.xres + x]; in write_vmem() local
296 u16 b = pixel & 0x1f; in write_vmem()
297 u16 g = (pixel & (0x3f << 5)) >> 5; in write_vmem()
298 u16 r = (pixel & (0x1f << (5 + 6))) >> (5 + 6); in write_vmem()
300 pixel = (299 * r + 587 * g + 114 * b) / 200; in write_vmem()
301 if (pixel > 255) in write_vmem()
302 pixel = 255; in write_vmem()
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H A Dfb_ssd1325.c61 static uint8_t rgb565_to_g16(u16 pixel) in rgb565_to_g16() argument
63 u16 b = pixel & 0x1f; in rgb565_to_g16()
64 u16 g = (pixel & (0x3f << 5)) >> 5; in rgb565_to_g16()
65 u16 r = (pixel & (0x1f << (5 + 6))) >> (5 + 6); in rgb565_to_g16()
67 pixel = (299 * r + 587 * g + 114 * b) / 195; in rgb565_to_g16()
68 if (pixel > 255) in rgb565_to_g16()
69 pixel = 255; in rgb565_to_g16()
70 return (uint8_t)pixel / 16; in rgb565_to_g16()
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-core.h83 * struct camif_fmt - pixel format description
88 * @depth: bits per pixel (total)
89 * @ybpp: number of luminance bytes per pixel
101 * struct camif_dma_offset - pixel offset information for DMA
102 * @initial: offset (in pixels) to first pixel
112 * @f_width: full pixel width
113 * @f_height: full pixel height
146 * @vp_pix_limits: pixel limits for the codec and preview paths
147 * @pix_limits: pixel limits for the camera input interface
199 * @out_fmt: pixel format at this video path output
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/linux/Documentation/fb/
H A Dpxafb.rst33 Pixel clock in picoseconds
63 4 or 8 pixel monochrome single panel data
72 Double pixel clock. 1=>true, 0=>false
80 pixel clock polarity
112 bpp = 16 -- for YUV422 planar (1 pixel = 1 Y + 1/2 Cb + 1/2 Cr)
114 bpp = 12 -- for YUV420 planar (1 pixel = 1 Y + 1/4 Cb + 1/4 Cr)
123 with minimum bits per pixel, e.g. for YUV420, Cr component
124 for one pixel is actually 2-bits, it means the line length
H A Dapi.rst47 to be aware of the pixel storage format in order to write image data to the
97 set to 0. When the number of bits per pixel is smaller than 8, several pixels
108 set to 1. When the number of bits per pixel is smaller than 8, several pixels
124 Pixel values are encoded as indices into a colormap that stores red, green and
128 Each pixel value is stored in the number of bits reported by the variable
198 __u32 nonstd; /* != 0 Non standard pixel format */
208 __u32 pixclock; /* pixel clock in ps (pico seconds) */
268 Pixel values are bits_per_pixel wide and are split in non-overlapping red,
270 component in the pixel value are described by the fb_bitfield offset and
274 bits per pixel is not a multiple of 8, pixel values are padded to the next
/linux/Documentation/userspace-api/media/drivers/
H A Dcamera-sensor.rst25 of cropping and scaling operations from the device's pixel array's size.
58 (analogue crop height + vertical blanking) / pixel rate
62 crop, use the full source image size, i.e. pixel array size.
66 is pixels and the unit of the ``V4L2_CID_VBLANK`` is lines. The pixel rate in
67 the sensor's **pixel array** is specified by ``V4L2_CID_PIXEL_RATE`` in the same
74 The first entity in the linear pipeline is the pixel array. The pixel array may
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h52 * Pixel Clock Parameters structure
54 * when calculating Pixel Clock Dividers for requested Pixel Clock
82 /*> Requested Pixel Clock
96 /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
103 * Pixel Clock Dividers structure with desired Pixel Clock
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.h49 * [23:20] RW dpi_color_mode: Define DPI pixel format. Default 0.
64 * 0=30-bit pixel;
65 * 1=24-bit pixel;
66 * 2=18-bit pixel, RGB666;
67 * 3=16-bit pixel, RGB565.
70 * 0=Use even pixel's chroma;
71 * 1=Use odd pixel's chroma;
99 /* DPI pixel format */
/linux/drivers/gpu/drm/stm/
H A Dltdc.h20 const u32 *pix_fmt_hw; /* supported hw pixel formats */
21 const u32 *pix_fmt_drm; /* supported drm pixel formats */
22 int pix_fmt_nb; /* number of pixel format */
23 bool pix_fmt_flex; /* pixel format flexibility supported */
46 struct clk *pixel_clk; /* lcd pixel clock */

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