Home
last modified time | relevance | path

Searched full:pio (Results 1 – 25 of 808) sorted by relevance

12345678910>>...33

/linux/drivers/pinctrl/
H A Dpinctrl-at91.c42 * @pioc_hwirq: PIO bank interrupt identifier on AIC
43 * @pioc_virq: PIO bank Linux virtual interrupt
44 * @regbase: PIO bank virtual address
190 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
191 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
192 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
193 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
194 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
195 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
196 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
[all …]
/linux/drivers/pinctrl/sunxi/
H A DKconfig15 bool "Support for the Allwinner A10, A20 and R40 PIO"
20 bool "Support for the Allwinner A10s, A13, R8 and NextThing GR8 PIO"
25 bool "Support for the Allwinner A31 PIO"
30 bool "Support for the Allwinner A31 R-PIO"
35 bool "Support for the Allwinner A23 PIO"
40 bool "Support for the Allwinner A33 PIO"
45 bool "Support for the Allwinner A83T PIO"
50 bool "Support for the Allwinner A83T R-PIO"
55 bool "Support for the Allwinner A23 and A33 R-PIO"
60 bool "Support for the Allwinner H3 PIO"
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dpio.c6 PIO Transmission
14 #include "pio.h"
109 /* We use the upper 4 bits for the PIO in generate_cookie()
140 struct b43legacy_pio *pio = &dev->pio; in parse_cookie() local
146 queue = pio->queue0; in parse_cookie()
149 queue = pio->queue1; in parse_cookie()
152 queue = pio->queue2; in parse_cookie()
155 queue = pio->queue3; in parse_cookie()
226 b43legacywarn(queue->dev->wl, "PIO queue too small. " in pio_tx_packet()
343 b43legacyerr(dev->wl, "This card does not support PIO " in b43legacy_setup_pioqueue()
[all …]
H A DKconfig75 bool "DMA + PIO"
79 Include both, Direct Memory Access (DMA) and Programmed I/O (PIO)
81 the module parameter "pio". With pio=0 as a module parameter, the
82 default DMA is used, otherwise PIO is used.
91 This reduces the size of the driver module, by omitting the PIO code.
94 bool "PIO (Programmed I/O) only"
97 Only include Programmed I/O (PIO).
99 Please note that PIO transfers are slow (compared to DMA).
101 Also note that not all devices of the b43legacy series support PIO.
103 You should use PIO only if DMA does not work for you.
/linux/drivers/net/wireless/broadcom/b43/
H A Dpio.c6 PIO data transfer
14 #include "pio.h"
30 * PIO controller ID and store the packet index number in generate_cookie()
48 struct b43_pio *pio = &dev->pio; in parse_cookie() local
54 q = pio->tx_queue_AC_BK; in parse_cookie()
57 q = pio->tx_queue_AC_BE; in parse_cookie()
60 q = pio->tx_queue_AC_VI; in parse_cookie()
63 q = pio->tx_queue_AC_VO; in parse_cookie()
66 q = pio->tx_queue_mcast; in parse_cookie()
172 /* Enable Direct FIFO RX (PIO) on the engine. */ in b43_setup_pioqueue_rx()
[all …]
/linux/drivers/ata/
H A Dpata_artop.c86 * artop6210_load_piomode - Load a set of PATA PIO timings
89 * @pio: PIO mode
91 * Set PIO mode for device, in host controller PCI config space. This
92 * is used both to set PIO timings in PIO mode and also to set the
93 * matching PIO clocking for UDMA, as well as the MWDMA timings.
99 static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio) in artop6210_load_piomode() argument
108 /* Load the PIO timing active/recovery bits */ in artop6210_load_piomode()
109 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); in artop6210_load_piomode()
113 * artop6210_set_piomode - Initialize host controller PATA PIO timings
117 * Set PIO mode for device, in host controller PCI config space. For
[all …]
H A Dpata_cs5520.c8 * PIO mode and smarter silicon.
11 * drive for the right PIO mode and ignore the drive bus mastering DMA
12 * information. Also to confuse matters further we can do DMA on PIO only
52 * cs5520_set_timings - program PIO timings
55 * @pio: PIO ID
57 * Program the PIO mode timings for the controller according to the pio
61 static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio) in cs5520_set_timings() argument
66 pio -= XFER_PIO_0; in cs5520_set_timings()
70 (cs5520_pio_clocks[pio].recovery << 4) | in cs5520_set_timings()
71 (cs5520_pio_clocks[pio].assert)); in cs5520_set_timings()
[all …]
H A Dpata_efar.c74 * efar_set_piomode - Initialize host controller PATA PIO timings
78 * Set PIO mode for device, in host controller PCI config space.
86 unsigned int pio = adev->pio_mode - XFER_PIO_0; in efar_set_piomode() local
106 if (pio > 1) in efar_set_piomode()
108 if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */ in efar_set_piomode()
122 master_data |= (timings[pio][0] << 12) | in efar_set_piomode()
123 (timings[pio][1] << 8); in efar_set_piomode()
134 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift; in efar_set_piomode()
193 * MWDMA is driven by the PIO timings. We must also enable in efar_set_dmamode()
195 * been set when the PIO timing was set. in efar_set_dmamode()
[all …]
H A Dpata_atiixp.c93 * atiixp_set_pio_timing - set initial PIO mode data
96 * @pio: Requested PIO
98 * Called by both the pio and dma setup functions to set the controller
99 * timings for PIO transfers. We must load both the mode number and
103 static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio) in atiixp_set_pio_timing() argument
115 pio_mode_data |= pio << (4 * dn); in atiixp_set_pio_timing()
120 pio_timing_data |= (pio_timings[pio] << timing_shift); in atiixp_set_pio_timing()
125 * atiixp_set_piomode - set initial PIO mode data
129 * Called to do the PIO mode setup. We use a shared helper for this
130 * as the DMA setup must also adjust the PIO timing information.
[all …]
H A Dpata_sl82c105.c14 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
16 * method as the PIO method is always called and will set the right PIO
68 * sl82c105_configure_piomode - set chip PIO timing
71 * @pio: PIO mode
73 * Called to do the PIO mode setup. Our timing registers are shared
78 static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) in sl82c105_configure_piomode() argument
87 pci_write_config_word(pdev, timing, pio_timing[pio]); in sl82c105_configure_piomode()
93 * sl82c105_set_piomode - set initial PIO mode data
97 * Called to do the PIO mode setup. Our timing registers are shared
98 * but we want to set the PIO timing by default.
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun4i-a10-inet9f-rev03.dts71 gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
79 gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
87 gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
95 gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
103 gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
111 gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
119 gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
127 gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
135 gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
143 gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
[all …]
H A Dsun7i-a20-cubietruck.dts80 gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
85 gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
90 gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>;
95 gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
101 reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */
202 cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
216 interrupt-parent = <&pio>;
234 &pio {
247 gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
287 gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>;
[all …]
H A Dsun7i-a20-olimex-som204-evb.dts51 gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
57 gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
63 gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
70 reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
159 reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
169 cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>;
197 &pio {
215 gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
254 gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
319 usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h700-anbernic-rg35xx-2024.dts39 gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
46 gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
53 gpios = <&pio 4 0 GPIO_ACTIVE_LOW>; /* PE0 */
60 gpios = <&pio 0 10 GPIO_ACTIVE_LOW>; /* PA10 */
67 gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
74 gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
81 gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
88 gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
95 gpios = <&pio 0 7 GPIO_ACTIVE_LOW>; /* PA7 */
102 gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
[all …]
/linux/arch/powerpc/include/asm/
H A Dio-defs.h23 DEF_PCI_AC_RET(inb, u8, (unsigned long port), (port), pio, port)
24 DEF_PCI_AC_RET(inw, u16, (unsigned long port), (port), pio, port)
25 DEF_PCI_AC_RET(inl, u32, (unsigned long port), (port), pio, port)
26 DEF_PCI_AC_NORET(outb, (u8 val, unsigned long port), (val, port), pio, port)
27 DEF_PCI_AC_NORET(outw, (u16 val, unsigned long port), (val, port), pio, port)
28 DEF_PCI_AC_NORET(outl, (u32 val, unsigned long port), (val, port), pio, port)
44 (p, b, c), pio, p)
46 (p, b, c), pio, p)
48 (p, b, c), pio, p)
50 (p, b, c), pio, p)
[all …]
/linux/tools/testing/selftests/kvm/
H A Dcoalesced_io_test.c87 * Annoyingly, reading PIO data is safe only for PIO exits, otherwise in vcpu_run_and_verify_io_exit()
103 "(PIO port = 0x%x, write = %u, len = %u, count = %u, data = %x", in vcpu_run_and_verify_io_exit()
104 ring_start, want_pio ? 4 : 8, want_pio ? "PIO" : "MMIO", in vcpu_run_and_verify_io_exit()
107 … run->exit_reason == KVM_EXIT_MMIO ? "MMIO" : run->exit_reason == KVM_EXIT_IO ? "PIO" : "other", in vcpu_run_and_verify_io_exit()
133 entry->len == 4 && entry->pio && in vcpu_run_and_verify_coalesced_io()
137 entry->len, entry->pio ? "PIO" : "MMIO", in vcpu_run_and_verify_coalesced_io()
142 entry->len == 8 && !entry->pio, in vcpu_run_and_verify_coalesced_io()
145 entry->len, entry->pio ? "PIO" : "MMIO", in vcpu_run_and_verify_coalesced_io()
155 kvm_vm_register_coalesced_io(vcpu->vm, io->mmio_gpa, 8, false /* pio */); in test_coalesced_io()
157 kvm_vm_register_coalesced_io(vcpu->vm, io->pio_port, 8, true /* pio */); in test_coalesced_io()
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7981b-cudy-wr3000-v1.dts24 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
30 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
41 gpios = <&pio 5 GPIO_ACTIVE_LOW>;
47 gpios = <&pio 6 GPIO_ACTIVE_LOW>;
53 gpios = <&pio 7 GPIO_ACTIVE_LOW>;
59 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
65 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
71 gpios = <&pio 11 GPIO_ACTIVE_LOW>;
H A Dmt7986a-bananapi-bpi-r3.dts56 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
62 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
69 sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
70 scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
79 sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
80 scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
92 gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
99 gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
128 los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
130 mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
[all …]
H A Dmt8186-corsola-steelix.dtsi19 gpio = <&pio 29 GPIO_ACTIVE_HIGH>;
30 gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
41 gpio = <&pio 31 GPIO_ACTIVE_HIGH>;
58 enable-gpios = <&pio 96 GPIO_ACTIVE_HIGH>;
59 reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
108 interrupts-extended = <&pio 12 IRQ_TYPE_EDGE_FALLING>;
111 reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
125 interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>;
160 &pio {
/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h77 #define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
95 volatile u32 pconfig; /* PIO configuration register */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
101 #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
102 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
103 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
125 #define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
137 #define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
138 #define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
139 #define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
[all …]
/linux/virt/kvm/
H A Dcoalesced_mmio.c74 ring->coalesced_mmio[insert].pio = dev->zone.pio; in coalesced_mmio_write()
128 if (zone->pio != 1 && zone->pio != 0) in kvm_vm_ioctl_register_coalesced_mmio()
142 zone->pio ? KVM_PIO_BUS : KVM_MMIO_BUS, in kvm_vm_ioctl_register_coalesced_mmio()
164 if (zone->pio != 1 && zone->pio != 0) in kvm_vm_ioctl_unregister_coalesced_mmio()
170 if (zone->pio == dev->zone.pio && in kvm_vm_ioctl_unregister_coalesced_mmio()
173 zone->pio ? KVM_PIO_BUS : KVM_MMIO_BUS, &dev->dev); in kvm_vm_ioctl_unregister_coalesced_mmio()
/linux/arch/mips/include/asm/sn/sn0/
H A Dhubni.h35 #define NI_VECTOR_PARMS 0x600200 /* Vector PIO routing parameters */
36 #define NI_VECTOR 0x600208 /* Vector PIO route */
37 #define NI_VECTOR_DATA 0x600210 /* Vector PIO data */
38 #define NI_VECTOR_STATUS 0x600300 /* Vector PIO return status */
39 #define NI_RETURN_VECTOR 0x600308 /* Vector PIO return vector */
40 #define NI_VECTOR_READ_DATA 0x600310 /* Vector PIO read data */
41 #define NI_VECTOR_CLEAR 0x600380 /* Vector PIO read & clear status */
43 #define NI_IO_PROTECT 0x600400 /* PIO protection bits */
44 #define NI_IO_PROT_OVRRD 0x600408 /* PIO protection bit override */
47 #define NI_AGE_CPU0_PIO 0x600508 /* CPU 0 PIO age control */
[all …]
/linux/drivers/soc/fsl/qe/
H A Dqe_io.c144 struct device_node *pio; in par_io_of_config() local
153 pio = of_parse_phandle(np, "pio-handle", 0); in par_io_of_config()
154 if (pio == NULL) { in par_io_of_config()
155 printk(KERN_ERR "pio-handle not available\n"); in par_io_of_config()
159 pio_map = of_get_property(pio, "pio-map", &pio_map_len); in par_io_of_config()
161 printk(KERN_ERR "pio-map is not set!\n"); in par_io_of_config()
166 printk(KERN_ERR "pio-map format wrong!\n"); in par_io_of_config()
183 of_node_put(pio); in par_io_of_config()
/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1-mangopi-mq-pro.dts31 gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
61 reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
79 cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
100 interrupt-parent = <&pio>;
110 &pio {
128 device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
129 enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
130 host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
/linux/Documentation/w1/slaves/
H A Dw1_ds28e04.rst7 * Maxim DS28E04-100 4096-Bit Addressable 1-Wire EEPROM with PIO
20 Support is provided through the sysfs files "eeprom" and "pio". CRC checking
35 PIO Access
37 The 2 PIOs of the DS28E04-100 are accessible via the "pio" sysfs file.
39 The current status of the PIO's is returned as an 8 bit value. Bit 0/1
40 represent the state of PIO_0/PIO_1. Bits 2..7 do not care. The PIO's are

12345678910>>...33