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/linux/Documentation/devicetree/bindings/leds/
H A Dkinetic,ktd2692.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markuss Broks <markuss.broks@gmail.com>
13 KTD2692 is the ideal power solution for high-power flash LEDs.
14 It uses ExpressWire single-wire programming for maximum flexibility.
16 The ExpressWire interface through CTRL pin can control LED on/off and
17 enable/disable the IC, Movie(max 1/3 of Flash current) / Flash mode current,
20 Also, When the AUX pin is pulled high while CTRL pin is high,
21 LED current will be ramped up to the flash-mode current level.
[all …]
/linux/drivers/net/ethernet/intel/igc/
H A Digc_ptp.c1 // SPDX-License-Identifier: GPL-2.0
27 struct igc_hw *hw = &adapter->hw; in igc_ptp_read()
34 ts->tv_sec = sec; in igc_ptp_read()
35 ts->tv_nsec = nsec; in igc_ptp_read()
41 struct igc_hw *hw = &adapter->hw; in igc_ptp_write_i225()
43 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
44 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
51 struct igc_hw *hw = &igc->hw; in igc_ptp_adjfine_i225()
58 scaled_ppm = -scaled_ppm; in igc_ptp_adjfine_i225()
80 spin_lock_irqsave(&igc->tmreg_lock, flags); in igc_ptp_adjtime_i225()
[all …]
/linux/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
45 /* Magic value to enable writes on jz4780 */
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
80 uint32_t ctrl; in jz4740_rtc_wait_write_ready() local
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
83 ctrl & JZ_RTC_CTRL_WRDY, 0, 1000); in jz4740_rtc_wait_write_ready()
88 uint32_t ctrl; in jz4780_rtc_enable_write() local
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
[all …]
/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A Digb_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
38 * +--------------+ +---+---+------+
40 * +--------------+ +---+---+------+
43 * +----------+---+ +--------------+
45 * +----------+---+ +--------------+
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
79 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82576()
96 struct e1000_hw *hw = &igb->hw; in igb_ptp_read_82580()
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c1 // SPDX-License-Identifier: GPL-2.0+
29 #include <linux/soc/samsung/exynos-pmu.h>
30 #include <linux/soc/samsung/exynos-regs-pmu.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
73 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
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/linux/drivers/tty/serial/
H A Drsci.c1 // SPDX-License-Identifier: GPL-2.0
46 #define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */
47 #define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */
48 #define CCR0_TIE BIT(20) /* Transmit Interrupt Enable */
49 #define CCR0_RIE BIT(16) /* Receive Interrupt Enable */
51 #define CCR0_DCME BIT(9) /* Data Compare Match Enable */
52 #define CCR0_MPIE BIT(8) /* Multiprocessor Interrupt Enable */
53 #define CCR0_TE BIT(4) /* Transmit Enable */
54 #define CCR0_RE BIT(0) /* Receive Enable */
58 #define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */
[all …]
H A Dmxs-auart.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
34 #include <linux/dma-mapping.h>
90 #define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
131 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
140 * input is idle, then the watchdog counter will decrement each bit-time. Note
141 * 7-bit-time is added to the programmed value, so a value of zero will set
142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-synology-ds213j.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-370.dtsi"
30 "marvell,armada-370-xp";
33 stdout-path = "serial0:115200n8";
[all …]
/linux/drivers/net/phy/
H A Dbcm-phy-ptp.c1 // SPDX-License-Identifier: GPL-2.0
16 #include "bcm-phy-lib.h"
134 struct ptp_pin_desc pin; member
158 #define BCM_SKB_CB(skb) ((struct bcm_ptp_skb_cb *)(skb)->cb)
161 #define BCM_MAX_PULSE_8NS ((1U << 9) - 1)
162 #define BCM_MAX_PERIOD_8NS ((1U << 30) - 1)
165 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
192 ts->tv_sec = (hb[3] << 16) | hb[2]; in bcm_ptp_get_framesync_ts()
193 ts->tv_nsec = (hb[1] << 16) | hb[0]; in bcm_ptp_get_framesync_ts()
198 u16 ctrl = orig_ctrl & ~(NSE_FRAMESYNC_MASK | NSE_CAPTURE_EN); in bcm_ptp_framesync_disable() local
[all …]
H A Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
129 * The value is calculated as following: (1/1000000)/((2^-32)/4)
135 * The value is calculated as following: (1/1000000)/((2^-32)/8)
189 #define PTP_GPIO_SEL_GPIO_SEL(pin) ((pin) << 8) argument
332 #define LAN8814_GPIO_EN_ADDR(pin) \ argument
333 ((pin) > 15 ? LAN8814_GPIO_EN1 : LAN8814_GPIO_EN2)
334 #define LAN8814_GPIO_EN_BIT(pin) BIT(pin) argument
335 #define LAN8814_GPIO_DIR_ADDR(pin) \ argument
336 ((pin) > 15 ? LAN8814_GPIO_DIR1 : LAN8814_GPIO_DIR2)
[all …]
/linux/arch/sparc/kernel/
H A Dleon_pci_grpci2.c1 // SPDX-License-Identifier: GPL-2.0
31 * - barcfgs : Custom Configuration of Host's 6 target BARs
32 * - irq_mask : Limit which PCI interrupts are enabled
33 * - do_reset : Force PCI Reset on startup
41 * -1 means not configured (let host driver do default setup).
50 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
65 /* Enable Debugging Configuration Space Access */
72 unsigned int ctrl; /* 0x00 Control */ member
79 unsigned int bars[6]; /* 0x20 read-only PCI BARs */
81 unsigned int ahbmst_map[16]; /* 0x40 AHB->PCI Map per AHB Master */
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,r9a09g077-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller.
14 Pin multiplexing and GPIO configuration are performed on a per-pin basis.
16 or alternate function mode. Each pin supports function mode values ranging from
22 - renesas,r9a09g077-pinctrl # RZ/T2H
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/linux/drivers/net/hamradio/
H A Dscc.c6 * Please use z8530drv-utils-3.0 with this version.
7 * ------------------
15 * SCC.C - Linux driver for Z8530 based HDLC cards for AX.25 *
28 The code is likely to fail, and so your kernel could --- even
40 For non-Amateur-Radio use please note that you might need a special
60 -------------------------------
62 1994-09-13 started to write the driver, rescued most of my own
71 1995-01-31 changed copyright notice to GPL without limitations.
77 1996-10-05 New semester, new driver...
85 * Invents brand new bugs... ;-)
[all …]
/linux/drivers/ptp/
H A Dptp_ocp.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/clk-provider.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
24 #include <linux/nvmem-consumer.h>
45 u32 ctrl; member
91 u32 ctrl; member
116 u32 enable; member
135 u32 ctrl; member
156 u32 ctrl; member
[all …]
/linux/drivers/net/ethernet/sfc/falcon/
H A Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
61 /* Enable bit */
69 /* Lane power-down */
108 /* Lane power-down */
125 /* Vendor-specific BIST registers */
[all …]
/linux/Documentation/core-api/
H A Ddebugging-via-ohci1394.rst2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
28 hardware such as x86, x86-64 and PowerPC.
34 Together with a early initialization of the OHCI-1394 controller for debugging,
41 -------
43 The firewire-ohci driver in drivers/firewire uses filtered physical
47 Because the firewire-ohci driver depends on the PCI enumeration to be
[all …]
/linux/drivers/phy/broadcom/
H A Dphy-brcm-usb-init-synopsys.c1 // SPDX-License-Identifier: GPL-2.0
13 #include "phy-brcm-usb-init.h"
36 /* Register definitions for the USB CTRL block */
110 void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO]; in usb_mdio_write_7211b0()
112 addr &= 0x1f; /* 5-bit address */ in usb_mdio_write_7211b0()
128 void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO]; in usb_mdio_read_7211b0()
130 addr &= 0x1f; /* 5-bit address */ in usb_mdio_read_7211b0()
155 void __iomem *ctrl = params->regs[BRCM_REGS_CTRL]; in xhci_soft_reset() local
156 void __iomem *xhci_gbl = params->regs[BRCM_REGS_XHCI_GBL]; in xhci_soft_reset()
160 USB_CTRL_UNSET(ctrl, USB_PM, XHC_SOFT_RESETB); in xhci_soft_reset()
[all …]
/linux/drivers/mfd/
H A Dti_am335x_tscadc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
33 spin_lock_irqsave(&tscadc->reg_lock, flags); in am335x_tsc_se_set_cache()
34 tscadc->reg_se_cache |= val; in am335x_tsc_se_set_cache()
35 if (tscadc->adc_waiting) in am335x_tsc_se_set_cache()
36 wake_up(&tscadc->reg_se_wait); in am335x_tsc_se_set_cache()
37 else if (!tscadc->adc_in_use) in am335x_tsc_se_set_cache()
38 regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); in am335x_tsc_se_set_cache()
40 spin_unlock_irqrestore(&tscadc->reg_lock, flags); in am335x_tsc_se_set_cache()
49 regmap_read(tscadc->regmap, REG_ADCFSM, &reg); in am335x_tscadc_need_adc()
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
154 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
156 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
246 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
[all …]
/linux/drivers/video/fbdev/omap/
H A Domapfb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
74 int acb; /* ac-bias pin frequency */
81 int (*enable) (struct lcd_panel *panel); member
105 u32 tim[5]; /* set by extif->convert_timings */
126 int (*enable_tearsync) (int enable, unsigned line);
166 int (*enable_plane) (int plane, int enable);
205 const struct lcd_ctrl *ctrl; /* LCD controller */ member
206 const struct lcd_ctrl *int_ctrl; /* internal LCD ctrl */
209 struct lcd_ctrl_extif *ext_if; /* LCD ctrl external
/linux/drivers/pinctrl/actions/
H A Dpinctrl-owl.h1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
28 .drv_reg = -1, \
29 .drv_shift = -1, \
30 .drv_width = -1, \
31 .sr_reg = -1, \
32 .sr_shift = -1, \
33 .sr_width = -1, \
41 .mfpctl_reg = -1, \
42 .mfpctl_shift = -1, \
[all …]
/linux/sound/sparc/
H A Ddbri.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
15 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
20 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
22 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
25 * - https://www.freesoft.org/Linux/DBRI/
26 * - MMCODE
84 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; global() variable
129 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */ global() member
[all...]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
18 stdout-path = "serial2:115200n8";
27 * - Rails that only connect to the EC (or devices that the EC talks to)
29 * - Rails _are_ included if the rails go to the AP even if the AP
38 * - The EC controls the enable and the EC always enables a rail as
40 * - The rails are actually connected to each other by a jumper and
45 ppvar_sys: regulator-ppvar-sys {
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dqcom,spmi-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/qcom,spmi-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robimarko@gmail.com>
15 - qcom,pm6125-regulators
16 - qcom,pm660-regulators
17 - qcom,pm660l-regulators
18 - qcom,pm8004-regulators
19 - qcom,pm8005-regulators
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