Lines Matching +full:pin +full:- +full:ctrl +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0+
29 #include <linux/soc/samsung/exynos-pmu.h>
30 #include <linux/soc/samsung/exynos-regs-pmu.h>
32 #include "pinctrl-samsung.h"
33 #include "pinctrl-exynos.h"
67 if (bank->eint_mask_offset) in exynos_irq_mask()
68 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
70 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
72 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
73 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
74 "unable to enable clock for masking IRQ\n"); in exynos_irq_mask()
78 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
80 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
81 mask |= 1 << irqd->hwirq; in exynos_irq_mask()
82 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
84 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
86 clk_disable(bank->drvdata->pclk); in exynos_irq_mask()
96 if (bank->eint_pend_offset) in exynos_irq_ack()
97 reg_pend = bank->pctl_offset + bank->eint_pend_offset; in exynos_irq_ack()
99 reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
101 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_ack()
102 dev_err(bank->gpio_chip.parent, in exynos_irq_ack()
103 "unable to enable clock to ack IRQ\n"); in exynos_irq_ack()
107 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
109 clk_disable(bank->drvdata->pclk); in exynos_irq_ack()
124 * If we don't do this we'll get a double-interrupt. Level triggered in exynos_irq_unmask()
132 if (bank->eint_mask_offset) in exynos_irq_unmask()
133 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_unmask()
135 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_unmask()
137 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_unmask()
138 dev_err(bank->gpio_chip.parent, in exynos_irq_unmask()
139 "unable to enable clock for unmasking IRQ\n"); in exynos_irq_unmask()
143 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_unmask()
145 mask = readl(bank->eint_base + reg_mask); in exynos_irq_unmask()
146 mask &= ~(1 << irqd->hwirq); in exynos_irq_unmask()
147 writel(mask, bank->eint_base + reg_mask); in exynos_irq_unmask()
149 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_unmask()
151 clk_disable(bank->drvdata->pclk); in exynos_irq_unmask()
159 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; in exynos_irq_set_type()
182 return -EINVAL; in exynos_irq_set_type()
190 if (bank->eint_con_offset) in exynos_irq_set_type()
191 reg_con = bank->pctl_offset + bank->eint_con_offset; in exynos_irq_set_type()
193 reg_con = our_chip->eint_con + bank->eint_offset; in exynos_irq_set_type()
195 ret = clk_enable(bank->drvdata->pclk); in exynos_irq_set_type()
197 dev_err(bank->gpio_chip.parent, in exynos_irq_set_type()
198 "unable to enable clock for configuring IRQ type\n"); in exynos_irq_set_type()
202 con = readl(bank->eint_base + reg_con); in exynos_irq_set_type()
205 writel(con, bank->eint_base + reg_con); in exynos_irq_set_type()
207 clk_disable(bank->drvdata->pclk); in exynos_irq_set_type()
216 struct samsung_pinctrl_drv_data *d = bank->drvdata; in exynos_irq_set_affinity()
217 struct irq_data *parent = irq_get_irq_data(d->irq); in exynos_irq_set_affinity()
220 return parent->chip->irq_set_affinity(parent, dest, force); in exynos_irq_set_affinity()
222 return -EINVAL; in exynos_irq_set_affinity()
228 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_request_resources()
233 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_request_resources()
235 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
236 "unable to lock pin %s-%lu IRQ\n", in exynos_irq_request_resources()
237 bank->name, irqd->hwirq); in exynos_irq_request_resources()
241 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_request_resources()
242 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; in exynos_irq_request_resources()
243 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; in exynos_irq_request_resources()
245 ret = clk_enable(bank->drvdata->pclk); in exynos_irq_request_resources()
247 dev_err(bank->gpio_chip.parent, in exynos_irq_request_resources()
248 "unable to enable clock for configuring pin %s-%lu\n", in exynos_irq_request_resources()
249 bank->name, irqd->hwirq); in exynos_irq_request_resources()
253 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_request_resources()
255 con = readl(bank->pctl_base + reg_con); in exynos_irq_request_resources()
258 writel(con, bank->pctl_base + reg_con); in exynos_irq_request_resources()
260 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_request_resources()
262 clk_disable(bank->drvdata->pclk); in exynos_irq_request_resources()
270 const struct samsung_pin_bank_type *bank_type = bank->type; in exynos_irq_release_resources()
274 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_release_resources()
275 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; in exynos_irq_release_resources()
276 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; in exynos_irq_release_resources()
278 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_release_resources()
279 dev_err(bank->gpio_chip.parent, in exynos_irq_release_resources()
280 "unable to enable clock for deconfiguring pin %s-%lu\n", in exynos_irq_release_resources()
281 bank->name, irqd->hwirq); in exynos_irq_release_resources()
285 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_release_resources()
287 con = readl(bank->pctl_base + reg_con); in exynos_irq_release_resources()
290 writel(con, bank->pctl_base + reg_con); in exynos_irq_release_resources()
292 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_release_resources()
294 clk_disable(bank->drvdata->pclk); in exynos_irq_release_resources()
296 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); in exynos_irq_release_resources()
322 struct samsung_pin_bank *b = h->host_data; in exynos_eint_irq_map()
325 irq_set_chip_and_handler(virq, &b->irq_chip->chip, in exynos_eint_irq_map()
341 struct samsung_pin_bank *bank = d->pin_banks; in exynos_eint_gpio_irq()
342 unsigned int svc, group, pin; in exynos_eint_gpio_irq() local
345 if (clk_enable(bank->drvdata->pclk)) { in exynos_eint_gpio_irq()
346 dev_err(bank->gpio_chip.parent, in exynos_eint_gpio_irq()
347 "unable to enable clock for handling IRQ\n"); in exynos_eint_gpio_irq()
351 if (bank->eint_con_offset) in exynos_eint_gpio_irq()
352 svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET); in exynos_eint_gpio_irq()
354 svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); in exynos_eint_gpio_irq()
356 clk_disable(bank->drvdata->pclk); in exynos_eint_gpio_irq()
359 pin = svc & EXYNOS_SVC_NUM_MASK; in exynos_eint_gpio_irq()
363 bank += (group - 1); in exynos_eint_gpio_irq()
365 ret = generic_handle_domain_irq(bank->irq_domain, pin); in exynos_eint_gpio_irq()
394 * Set the desired filter (digital or analog delay) and enable it to
395 * every pin in the bank. Note the filter selection bitfield is only
401 unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offset; in exynos_eint_set_filter()
402 void __iomem *reg = bank->drvdata->virt_base + off; in exynos_eint_set_filter()
405 for (int n = 0; n < bank->nr_pins; n += 4) in exynos_eint_set_filter()
407 min(bank->nr_pins - n, 4), con); in exynos_eint_set_filter()
411 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
417 struct device *dev = d->dev; in exynos_eint_gpio_init()
421 if (!d->irq) { in exynos_eint_gpio_init()
423 return -EINVAL; in exynos_eint_gpio_init()
426 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, in exynos_eint_gpio_init()
430 return -ENXIO; in exynos_eint_gpio_init()
433 bank = d->pin_banks; in exynos_eint_gpio_init()
434 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_gpio_init()
435 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
438 bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip, in exynos_eint_gpio_init()
439 sizeof(*bank->irq_chip), GFP_KERNEL); in exynos_eint_gpio_init()
440 if (!bank->irq_chip) { in exynos_eint_gpio_init()
441 ret = -ENOMEM; in exynos_eint_gpio_init()
444 bank->irq_chip->chip.name = bank->name; in exynos_eint_gpio_init()
446 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_gpio_init()
447 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_gpio_init()
448 if (!bank->irq_domain) { in exynos_eint_gpio_init()
450 ret = -ENXIO; in exynos_eint_gpio_init()
454 bank->soc_priv = devm_kzalloc(d->dev, in exynos_eint_gpio_init()
456 if (!bank->soc_priv) { in exynos_eint_gpio_init()
457 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
458 ret = -ENOMEM; in exynos_eint_gpio_init()
467 for (--i, --bank; i >= 0; --i, --bank) { in exynos_eint_gpio_init()
468 if (bank->eint_type != EINT_TYPE_GPIO) in exynos_eint_gpio_init()
470 irq_domain_remove(bank->irq_domain); in exynos_eint_gpio_init()
480 struct samsung_pinctrl_drv_data *d = bank->drvdata; in gs101_wkup_irq_set_wake()
483 bit = bank->eint_num + irqd->hwirq; in gs101_wkup_irq_set_wake()
485 shift = bit - (wakeup_reg * BITS_PER_U32); in gs101_wkup_irq_set_wake()
492 dev_info(d->dev, "wake %s for irq %d\n", str_enabled_disabled(on), in gs101_wkup_irq_set_wake()
493 irqd->irq); in gs101_wkup_irq_set_wake()
504 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { in gs101_pinctrl_set_eint_wakeup_mask()
505 dev_warn(drvdata->dev, in gs101_pinctrl_set_eint_wakeup_mask()
506 "No PMU syscon available. Wake-up mask will not be set.\n"); in gs101_pinctrl_set_eint_wakeup_mask()
510 pmu_regs = drvdata->retention_ctrl->priv; in gs101_pinctrl_set_eint_wakeup_mask()
512 dev_dbg(drvdata->dev, "Setting external wakeup interrupt mask:\n"); in gs101_pinctrl_set_eint_wakeup_mask()
514 for (int i = 0; i < irq_chip->eint_num_wakeup_reg; i++) { in gs101_pinctrl_set_eint_wakeup_mask()
515 dev_dbg(drvdata->dev, "\tWAKEUP_MASK%d[0x%X] value[0x%X]\n", in gs101_pinctrl_set_eint_wakeup_mask()
516 i, irq_chip->eint_wake_mask_reg + i * 4, in gs101_pinctrl_set_eint_wakeup_mask()
518 regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg + i * 4, in gs101_pinctrl_set_eint_wakeup_mask()
526 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); in exynos_wkup_irq_set_wake()
528 pr_info("wake %s for irq %u (%s-%lu)\n", str_enabled_disabled(on), in exynos_wkup_irq_set_wake()
529 irqd->irq, bank->name, irqd->hwirq); in exynos_wkup_irq_set_wake()
545 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { in exynos_pinctrl_set_eint_wakeup_mask()
546 dev_warn(drvdata->dev, in exynos_pinctrl_set_eint_wakeup_mask()
547 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in exynos_pinctrl_set_eint_wakeup_mask()
551 pmu_regs = drvdata->retention_ctrl->priv; in exynos_pinctrl_set_eint_wakeup_mask()
552 dev_info(drvdata->dev, in exynos_pinctrl_set_eint_wakeup_mask()
556 regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, in exynos_pinctrl_set_eint_wakeup_mask()
567 if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { in s5pv210_pinctrl_set_eint_wakeup_mask()
568 dev_warn(drvdata->dev, in s5pv210_pinctrl_set_eint_wakeup_mask()
569 …"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n… in s5pv210_pinctrl_set_eint_wakeup_mask()
574 clk_base = (void __iomem *) drvdata->retention_ctrl->priv; in s5pv210_pinctrl_set_eint_wakeup_mask()
577 clk_base + irq_chip->eint_wake_mask_reg); in s5pv210_pinctrl_set_eint_wakeup_mask()
678 { .compatible = "google,gs101-wakeup-eint",
680 { .compatible = "samsung,s5pv210-wakeup-eint",
682 { .compatible = "samsung,exynos4210-wakeup-eint",
684 { .compatible = "samsung,exynos7-wakeup-eint",
686 { .compatible = "samsung,exynos850-wakeup-eint",
688 { .compatible = "samsung,exynosautov9-wakeup-eint",
690 { .compatible = "samsung,exynosautov920-wakeup-eint",
699 struct samsung_pin_bank *bank = eintd->bank; in exynos_irq_eint0_15()
704 generic_handle_domain_irq(bank->irq_domain, eintd->irq); in exynos_irq_eint0_15()
715 irq = fls(pend) - 1; in exynos_irq_demux_eint()
733 * just enable the clock once here, to avoid an enable/disable dance for in exynos_irq_demux_eint16_31()
736 if (eintd->nr_banks) { in exynos_irq_demux_eint16_31()
737 struct samsung_pin_bank *b = eintd->banks[0]; in exynos_irq_demux_eint16_31()
739 if (clk_enable(b->drvdata->pclk)) { in exynos_irq_demux_eint16_31()
740 dev_err(b->gpio_chip.parent, in exynos_irq_demux_eint16_31()
741 "unable to enable clock for pending IRQs\n"); in exynos_irq_demux_eint16_31()
746 for (i = 0; i < eintd->nr_banks; ++i) { in exynos_irq_demux_eint16_31()
747 struct samsung_pin_bank *b = eintd->banks[i]; in exynos_irq_demux_eint16_31()
748 pend = readl(b->eint_base + b->irq_chip->eint_pend in exynos_irq_demux_eint16_31()
749 + b->eint_offset); in exynos_irq_demux_eint16_31()
750 mask = readl(b->eint_base + b->irq_chip->eint_mask in exynos_irq_demux_eint16_31()
751 + b->eint_offset); in exynos_irq_demux_eint16_31()
752 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); in exynos_irq_demux_eint16_31()
755 if (eintd->nr_banks) in exynos_irq_demux_eint16_31()
756 clk_disable(eintd->banks[0]->drvdata->pclk); in exynos_irq_demux_eint16_31()
764 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
769 struct device *dev = d->dev; in exynos_eint_wkup_init()
780 for_each_child_of_node(dev->of_node, np) { in exynos_eint_wkup_init()
785 irq_chip = match->data; in exynos_eint_wkup_init()
791 return -ENODEV; in exynos_eint_wkup_init()
793 bank = d->pin_banks; in exynos_eint_wkup_init()
794 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
795 if (bank->eint_type != EINT_TYPE_WKUP) in exynos_eint_wkup_init()
798 bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip), in exynos_eint_wkup_init()
800 if (!bank->irq_chip) in exynos_eint_wkup_init()
801 return -ENOMEM; in exynos_eint_wkup_init()
802 bank->irq_chip->chip.name = bank->name; in exynos_eint_wkup_init()
804 bank->irq_domain = irq_domain_create_linear(bank->fwnode, in exynos_eint_wkup_init()
805 bank->nr_pins, &exynos_eint_irqd_ops, bank); in exynos_eint_wkup_init()
806 if (!bank->irq_domain) { in exynos_eint_wkup_init()
808 return -ENXIO; in exynos_eint_wkup_init()
811 bank->eint_num = eint_num; in exynos_eint_wkup_init()
812 eint_num = eint_num + bank->nr_pins; in exynos_eint_wkup_init()
814 if (!fwnode_property_present(bank->fwnode, "interrupts")) { in exynos_eint_wkup_init()
815 bank->eint_type = EINT_TYPE_WKUP_MUX; in exynos_eint_wkup_init()
821 bank->nr_pins, sizeof(*weint_data), in exynos_eint_wkup_init()
824 return -ENOMEM; in exynos_eint_wkup_init()
826 for (idx = 0; idx < bank->nr_pins; ++idx) { in exynos_eint_wkup_init()
827 irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx); in exynos_eint_wkup_init()
829 dev_err(dev, "irq number for eint-%s-%d not found\n", in exynos_eint_wkup_init()
830 bank->name, idx); in exynos_eint_wkup_init()
853 return -ENOMEM; in exynos_eint_wkup_init()
854 muxed_data->nr_banks = muxed_banks; in exynos_eint_wkup_init()
859 bank = d->pin_banks; in exynos_eint_wkup_init()
861 for (i = 0; i < d->nr_banks; ++i, ++bank) { in exynos_eint_wkup_init()
862 if (bank->eint_type != EINT_TYPE_WKUP_MUX) in exynos_eint_wkup_init()
865 muxed_data->banks[idx++] = bank; in exynos_eint_wkup_init()
875 if (bank->irq_chip) { in exynos_set_wakeup()
876 irq_chip = bank->irq_chip; in exynos_set_wakeup()
877 irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip); in exynos_set_wakeup()
883 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_suspend()
884 const void __iomem *regs = bank->eint_base; in exynos_pinctrl_suspend()
886 if (bank->eint_type == EINT_TYPE_GPIO) { in exynos_pinctrl_suspend()
887 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET in exynos_pinctrl_suspend()
888 + bank->eint_offset); in exynos_pinctrl_suspend()
889 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_suspend()
890 + 2 * bank->eint_offset); in exynos_pinctrl_suspend()
891 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_suspend()
892 + 2 * bank->eint_offset + 4); in exynos_pinctrl_suspend()
893 save->eint_mask = readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_suspend()
894 + bank->eint_offset); in exynos_pinctrl_suspend()
897 bank->name, save->eint_con); in exynos_pinctrl_suspend()
899 bank->name, save->eint_fltcon0); in exynos_pinctrl_suspend()
901 bank->name, save->eint_fltcon1); in exynos_pinctrl_suspend()
903 bank->name, save->eint_mask); in exynos_pinctrl_suspend()
904 } else if (bank->eint_type == EINT_TYPE_WKUP) { in exynos_pinctrl_suspend()
911 struct exynos_eint_gpio_save *save = bank->soc_priv; in gs101_pinctrl_suspend()
912 const void __iomem *regs = bank->eint_base; in gs101_pinctrl_suspend()
914 if (bank->eint_type == EINT_TYPE_GPIO) { in gs101_pinctrl_suspend()
915 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET in gs101_pinctrl_suspend()
916 + bank->eint_offset); in gs101_pinctrl_suspend()
918 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET in gs101_pinctrl_suspend()
919 + bank->eint_fltcon_offset); in gs101_pinctrl_suspend()
921 /* fltcon1 register only exists for pins 4-7 */ in gs101_pinctrl_suspend()
922 if (bank->nr_pins > 4) in gs101_pinctrl_suspend()
923 save->eint_fltcon1 = readl(regs + in gs101_pinctrl_suspend()
925 + bank->eint_fltcon_offset + 4); in gs101_pinctrl_suspend()
927 save->eint_mask = readl(regs + bank->irq_chip->eint_mask in gs101_pinctrl_suspend()
928 + bank->eint_offset); in gs101_pinctrl_suspend()
931 bank->name, save->eint_con); in gs101_pinctrl_suspend()
933 bank->name, save->eint_fltcon0); in gs101_pinctrl_suspend()
934 if (bank->nr_pins > 4) in gs101_pinctrl_suspend()
936 bank->name, save->eint_fltcon1); in gs101_pinctrl_suspend()
938 bank->name, save->eint_mask); in gs101_pinctrl_suspend()
939 } else if (bank->eint_type == EINT_TYPE_WKUP) { in gs101_pinctrl_suspend()
947 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynosautov920_pinctrl_suspend()
948 const void __iomem *regs = bank->eint_base; in exynosautov920_pinctrl_suspend()
950 if (bank->eint_type == EINT_TYPE_GPIO) { in exynosautov920_pinctrl_suspend()
951 save->eint_con = readl(regs + bank->pctl_offset + in exynosautov920_pinctrl_suspend()
952 bank->eint_con_offset); in exynosautov920_pinctrl_suspend()
953 save->eint_mask = readl(regs + bank->pctl_offset + in exynosautov920_pinctrl_suspend()
954 bank->eint_mask_offset); in exynosautov920_pinctrl_suspend()
956 bank->name, save->eint_con); in exynosautov920_pinctrl_suspend()
958 bank->name, save->eint_mask); in exynosautov920_pinctrl_suspend()
959 } else if (bank->eint_type == EINT_TYPE_WKUP) { in exynosautov920_pinctrl_suspend()
966 struct exynos_eint_gpio_save *save = bank->soc_priv; in gs101_pinctrl_resume()
968 void __iomem *regs = bank->eint_base; in gs101_pinctrl_resume()
970 + bank->eint_fltcon_offset; in gs101_pinctrl_resume()
972 if (bank->eint_type == EINT_TYPE_GPIO) { in gs101_pinctrl_resume()
973 pr_debug("%s: con %#010x => %#010x\n", bank->name, in gs101_pinctrl_resume()
975 + bank->eint_offset), save->eint_con); in gs101_pinctrl_resume()
977 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, in gs101_pinctrl_resume()
978 readl(eint_fltcfg0), save->eint_fltcon0); in gs101_pinctrl_resume()
980 /* fltcon1 register only exists for pins 4-7 */ in gs101_pinctrl_resume()
981 if (bank->nr_pins > 4) in gs101_pinctrl_resume()
982 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, in gs101_pinctrl_resume()
983 readl(eint_fltcfg0 + 4), save->eint_fltcon1); in gs101_pinctrl_resume()
985 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in gs101_pinctrl_resume()
986 readl(regs + bank->irq_chip->eint_mask in gs101_pinctrl_resume()
987 + bank->eint_offset), save->eint_mask); in gs101_pinctrl_resume()
989 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET in gs101_pinctrl_resume()
990 + bank->eint_offset); in gs101_pinctrl_resume()
991 writel(save->eint_fltcon0, eint_fltcfg0); in gs101_pinctrl_resume()
993 if (bank->nr_pins > 4) in gs101_pinctrl_resume()
994 writel(save->eint_fltcon1, eint_fltcfg0 + 4); in gs101_pinctrl_resume()
995 writel(save->eint_mask, regs + bank->irq_chip->eint_mask in gs101_pinctrl_resume()
996 + bank->eint_offset); in gs101_pinctrl_resume()
997 } else if (bank->eint_type == EINT_TYPE_WKUP) { in gs101_pinctrl_resume()
1004 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_resume()
1005 void __iomem *regs = bank->eint_base; in exynos_pinctrl_resume()
1007 if (bank->eint_type == EINT_TYPE_GPIO) { in exynos_pinctrl_resume()
1008 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume()
1010 + bank->eint_offset), save->eint_con); in exynos_pinctrl_resume()
1011 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume()
1013 + 2 * bank->eint_offset), save->eint_fltcon0); in exynos_pinctrl_resume()
1014 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume()
1016 + 2 * bank->eint_offset + 4), in exynos_pinctrl_resume()
1017 save->eint_fltcon1); in exynos_pinctrl_resume()
1018 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynos_pinctrl_resume()
1019 readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume()
1020 + bank->eint_offset), save->eint_mask); in exynos_pinctrl_resume()
1022 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET in exynos_pinctrl_resume()
1023 + bank->eint_offset); in exynos_pinctrl_resume()
1024 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_resume()
1025 + 2 * bank->eint_offset); in exynos_pinctrl_resume()
1026 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_resume()
1027 + 2 * bank->eint_offset + 4); in exynos_pinctrl_resume()
1028 writel(save->eint_mask, regs + bank->irq_chip->eint_mask in exynos_pinctrl_resume()
1029 + bank->eint_offset); in exynos_pinctrl_resume()
1035 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynosautov920_pinctrl_resume()
1036 void __iomem *regs = bank->eint_base; in exynosautov920_pinctrl_resume()
1038 if (bank->eint_type == EINT_TYPE_GPIO) { in exynosautov920_pinctrl_resume()
1040 if (!bank->eint_con_offset) in exynosautov920_pinctrl_resume()
1043 pr_debug("%s: con %#010x => %#010x\n", bank->name, in exynosautov920_pinctrl_resume()
1044 readl(regs + bank->pctl_offset + bank->eint_con_offset), in exynosautov920_pinctrl_resume()
1045 save->eint_con); in exynosautov920_pinctrl_resume()
1046 pr_debug("%s: mask %#010x => %#010x\n", bank->name, in exynosautov920_pinctrl_resume()
1047 readl(regs + bank->pctl_offset + in exynosautov920_pinctrl_resume()
1048 bank->eint_mask_offset), save->eint_mask); in exynosautov920_pinctrl_resume()
1050 writel(save->eint_con, in exynosautov920_pinctrl_resume()
1051 regs + bank->pctl_offset + bank->eint_con_offset); in exynosautov920_pinctrl_resume()
1052 writel(save->eint_mask, in exynosautov920_pinctrl_resume()
1053 regs + bank->pctl_offset + bank->eint_mask_offset); in exynosautov920_pinctrl_resume()
1059 if (drvdata->retention_ctrl->refcnt) in exynos_retention_enable()
1060 atomic_inc(drvdata->retention_ctrl->refcnt); in exynos_retention_enable()
1065 struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl; in exynos_retention_disable() local
1066 struct regmap *pmu_regs = ctrl->priv; in exynos_retention_disable()
1069 if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt)) in exynos_retention_disable()
1072 for (i = 0; i < ctrl->nr_regs; i++) in exynos_retention_disable()
1073 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); in exynos_retention_disable()
1080 struct samsung_retention_ctrl *ctrl; in exynos_retention_init() local
1084 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in exynos_retention_init()
1085 if (!ctrl) in exynos_retention_init()
1086 return ERR_PTR(-ENOMEM); in exynos_retention_init()
1092 ctrl->priv = pmu_regs; in exynos_retention_init()
1093 ctrl->regs = data->regs; in exynos_retention_init()
1094 ctrl->nr_regs = data->nr_regs; in exynos_retention_init()
1095 ctrl->value = data->value; in exynos_retention_init()
1096 ctrl->refcnt = data->refcnt; in exynos_retention_init()
1097 ctrl->enable = exynos_retention_enable; in exynos_retention_init()
1098 ctrl->disable = exynos_retention_disable; in exynos_retention_init()
1101 for (i = 0; i < ctrl->nr_regs; i++) in exynos_retention_init()
1102 regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); in exynos_retention_init()
1104 return ctrl; in exynos_retention_init()