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/linux/arch/arm/mach-s3c/
H A Dsetup-usb-phy-s3c64xx.c26 u32 phyclk; in s3c_usb_otgphy_init() local
31 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; in s3c_usb_otgphy_init()
37 phyclk |= S3C_PHYCLK_CLKSEL_12M; in s3c_usb_otgphy_init()
40 phyclk |= S3C_PHYCLK_CLKSEL_24M; in s3c_usb_otgphy_init()
51 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); in s3c_usb_otgphy_init()
/linux/drivers/phy/samsung/
H A Dphy-exynos5250-sata.c50 struct clk *phyclk; member
196 sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl"); in exynos_sata_phy_probe()
197 if (IS_ERR(sata_phy->phyclk)) { in exynos_sata_phy_probe()
199 ret = PTR_ERR(sata_phy->phyclk); in exynos_sata_phy_probe()
203 ret = clk_prepare_enable(sata_phy->phyclk); in exynos_sata_phy_probe()
228 clk_disable_unprepare(sata_phy->phyclk); in exynos_sata_phy_probe()
/linux/Documentation/devicetree/bindings/phy/
H A Drockchip,inno-usb2phy.yaml46 - const: phyclk
231 clock-names = "phyclk";
H A Drockchip-usb-phy.yaml47 const: phyclk
/linux/drivers/net/wireless/ath/ath10k/
H A Dhw.c602 u32 phyclk; in ath10k_hw_qca988x_set_coverage_class() local
627 phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1; in ath10k_hw_qca988x_set_coverage_class()
653 if (slottime_reg % phyclk) { in ath10k_hw_qca988x_set_coverage_class()
661 slottime = slottime / phyclk; in ath10k_hw_qca988x_set_coverage_class()
675 slottime += value * 3 * phyclk; in ath10k_hw_qca988x_set_coverage_class()
682 ack_timeout += 3 * value * phyclk; in ath10k_hw_qca988x_set_coverage_class()
688 cts_timeout += 3 * value * phyclk; in ath10k_hw_qca988x_set_coverage_class()
/linux/drivers/phy/freescale/
H A Dphy-fsl-samsung-hdmi.c612 struct clk *phyclk; in phy_clk_register() local
625 phyclk = devm_clk_register(dev, &phy->hw); in phy_clk_register()
626 if (IS_ERR(phyclk)) in phy_clk_register()
627 return dev_err_probe(dev, PTR_ERR(phyclk), in phy_clk_register()
630 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk); in phy_clk_register()
/linux/Documentation/devicetree/bindings/net/
H A Dsti-dwmac.txt20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
H A Dstm32-dwmac.yaml102 st,ext-phyclk:
/linux/arch/arm/boot/dts/st/
H A Dstm32mp135f-dhcor-dhsbc.dts85 st,ext-phyclk;
134 st,ext-phyclk;
H A Dstih407-pinctrl.dtsi218 phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
260 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
281 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
287 phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
/linux/Documentation/devicetree/bindings/usb/
H A Dsamsung,exynos-dwc3.yaml127 - const: phyclk
/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,flexgen.txt125 "clk-eth-ref-phyclk",
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c159 /* PHYCLK */ in dcn3_init_clocks()
465 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/
H A Ddcn4_soc_bb.h110 .phyclk = {
/linux/drivers/usb/dwc3/
H A Ddwc3-exynos.c161 .clk_names = { "aclk", "susp_clk", "pipe_pclk", "phyclk" },
/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a.dtsi715 clock-names = "phyclk";
723 clock-names = "phyclk";
H A Drk3188.dtsi657 clock-names = "phyclk";
665 clock-names = "phyclk";
H A Drk3288.dtsi915 clock-names = "phyclk";
925 clock-names = "phyclk";
935 clock-names = "phyclk";
H A Drk322x.dtsi259 clock-names = "phyclk";
286 clock-names = "phyclk";
/linux/drivers/clk/st/
H A Dclk-flexgen.c350 { .name = "clk-eth-ref-phyclk", },
405 { .name = "clk-eth-ref-phyclk", },
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h311 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml364 clock-names = "phyclk";
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dd11.h1746 #define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
1747 #define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
1748 #define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c492 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c544 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */

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