| /linux/arch/arm/mach-s3c/ |
| H A D | setup-usb-phy-s3c64xx.c | 26 u32 phyclk; in s3c_usb_otgphy_init() local
31 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; in s3c_usb_otgphy_init()
37 phyclk |= S3C_PHYCLK_CLKSEL_12M; in s3c_usb_otgphy_init()
40 phyclk |= S3C_PHYCLK_CLKSEL_24M; in s3c_usb_otgphy_init()
51 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); in s3c_usb_otgphy_init()
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| /linux/drivers/phy/samsung/ |
| H A D | phy-exynos5250-sata.c | 50 struct clk *phyclk; member
196 sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl"); in exynos_sata_phy_probe()
197 if (IS_ERR(sata_phy->phyclk)) { in exynos_sata_phy_probe()
199 ret = PTR_ERR(sata_phy->phyclk); in exynos_sata_phy_probe()
203 ret = clk_prepare_enable(sata_phy->phyclk); in exynos_sata_phy_probe()
228 clk_disable_unprepare(sata_phy->phyclk); in exynos_sata_phy_probe()
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | rockchip,inno-usb2phy.yaml | 46 - const: phyclk
231 clock-names = "phyclk";
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| H A D | rockchip-usb-phy.yaml | 47 const: phyclk
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| /linux/drivers/net/wireless/ath/ath10k/ |
| H A D | hw.c | 602 u32 phyclk; in ath10k_hw_qca988x_set_coverage_class() local
627 phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1; in ath10k_hw_qca988x_set_coverage_class()
653 if (slottime_reg % phyclk) { in ath10k_hw_qca988x_set_coverage_class()
661 slottime = slottime / phyclk; in ath10k_hw_qca988x_set_coverage_class()
675 slottime += value * 3 * phyclk; in ath10k_hw_qca988x_set_coverage_class()
682 ack_timeout += 3 * value * phyclk; in ath10k_hw_qca988x_set_coverage_class()
688 cts_timeout += 3 * value * phyclk; in ath10k_hw_qca988x_set_coverage_class()
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | sti-dwmac.txt | 20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
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| H A D | stm32-dwmac.yaml | 102 st,ext-phyclk:
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp135f-dhcor-dhsbc.dts | 85 st,ext-phyclk;
134 st,ext-phyclk;
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| H A D | stih407-pinctrl.dtsi | 218 phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
260 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
281 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
287 phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | samsung,exynos-dwc3.yaml | 133 - const: phyclk
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/ |
| H A D | dcn42_soc_bb.h | 101 .phyclk = {
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| /linux/Documentation/devicetree/bindings/clock/st/ |
| H A D | st,flexgen.txt | 125 "clk-eth-ref-phyclk",
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| /linux/drivers/usb/dwc3/ |
| H A D | dwc3-exynos.c | 161 .clk_names = { "aclk", "susp_clk", "pipe_pclk", "phyclk" },
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3066a.dtsi | 715 clock-names = "phyclk";
723 clock-names = "phyclk";
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| H A D | rk3188.dtsi | 657 clock-names = "phyclk";
665 clock-names = "phyclk";
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| H A D | rk322x.dtsi | 259 clock-names = "phyclk";
286 clock-names = "phyclk";
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| H A D | rv1108.dtsi | 265 clock-names = "phyclk";
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| H A D | rk3128.dtsi | 564 clock-names = "phyclk";
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| /linux/drivers/clk/st/ |
| H A D | clk-flexgen.c | 350 { .name = "clk-eth-ref-phyclk", },
405 { .name = "clk-eth-ref-phyclk", },
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| /linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| H A D | d11.h | 1746 #define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
1747 #define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
1748 #define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 492 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/ |
| H A D | dml21_translation_helper.c | 985 …min_clocks->phyclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.phyclk.clk_values_khz[lowest_dpm_st… in dml21_init_min_clocks_for_dc_state()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega12_hwmgr.c | 766 /* phyclk */ in vega12_setup_default_dpm_tables()
771 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", in vega12_setup_default_dpm_tables()
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| H A D | vega20_hwmgr.c | 753 /* phyclk */ in vega20_setup_default_dpm_tables()
758 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", in vega20_setup_default_dpm_tables()
1655 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!", in vega20_init_max_sustainable_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/ |
| H A D | dml2_dpmm_dcn4.c | 442 …phyclk_khz, &display_cfg->stream_programming[i].min_clocks.dcn4x.phyclk_khz, &state_table->phyclk); in map_min_clocks_to_dpm()
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