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/linux/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.h110 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro
112 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
113 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
120 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
121 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
122 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
123 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
124 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
139 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
140 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
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H A Dich8lan.c178 u16 phy_reg = 0; in e1000_phy_is_accessible_pchlan() local
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); in e1000_phy_is_accessible_pchlan()
186 if (ret_val || (phy_reg == 0xFFFF)) in e1000_phy_is_accessible_pchlan()
188 phy_id = (u32)(phy_reg << 16); in e1000_phy_is_accessible_pchlan()
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); in e1000_phy_is_accessible_pchlan()
191 if (ret_val || (phy_reg == 0xFFFF)) { in e1000_phy_is_accessible_pchlan()
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_phy_is_accessible_pchlan()
232 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; in e1000_phy_is_accessible_pchlan()
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H A Dphy.h48 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
49 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
H A Dphy.c2581 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2583 * Assumes semaphore already acquired and phy_reg points to a valid memory
2586 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) in e1000_enable_phy_wakeup_reg_access_bm() argument
2601 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); in e1000_enable_phy_wakeup_reg_access_bm()
2611 temp = *phy_reg; in e1000_enable_phy_wakeup_reg_access_bm()
2631 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2635 * Assumes semaphore already acquired and *phy_reg is the contents of the
2639 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) in e1000_disable_phy_wakeup_reg_access_bm() argument
2651 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); in e1000_disable_phy_wakeup_reg_access_bm()
2690 u16 phy_reg = 0; in e1000_access_phy_wakeup_reg_bm() local
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H A Dnetdev.c3084 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); in e1000_setup_rctl()
3087 e1e_wphy(hw, PHY_REG(770, 26), phy_data); in e1000_setup_rctl()
6234 u16 phy_reg, wuc_enable; in e1000_init_phy_wakeup() local
6261 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); in e1000_init_phy_wakeup()
6264 phy_reg |= BM_RCTL_UPE; in e1000_init_phy_wakeup()
6266 phy_reg |= BM_RCTL_MPE; in e1000_init_phy_wakeup()
6267 phy_reg &= ~(BM_RCTL_MO_MASK); in e1000_init_phy_wakeup()
6269 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg) in e1000_init_phy_wakeup()
6272 phy_reg |= BM_RCTL_BAM; in e1000_init_phy_wakeup()
6274 phy_reg |= BM_RCTL_PMCF; in e1000_init_phy_wakeup()
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H A Dregs.h243 #define I82579_DFT_CTRL PHY_REG(769, 20)
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c109 #define PHY_REG(_offset, _width, _shift) \ macro
113 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
114 [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
115 [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
116 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
117 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
118 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
119 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
120 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
121 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
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H A Dphy-rockchip-inno-csidphy.c101 #define PHY_REG(_offset, _width, _shift) \ macro
105 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
106 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
107 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
111 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
112 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
113 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
117 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
121 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3568_GRF_VI_CON0, 4, 0),
122 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 4, 4),
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H A Dphy-rockchip-inno-dsidphy.c37 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ macro
327 u32 reg = PHY_REG(first, second) << 2; in phy_update_bits()
/linux/drivers/phy/freescale/
H A Dphy-fsl-samsung-hdmi.c17 #define PHY_REG(reg) (reg * 4) macro
285 { PHY_REG(0), 0x00 },
286 /* PHY_REG(1-7) pix clk specific */
287 { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 },
288 { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 },
292 { PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c },
293 { PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 },
294 { PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 },
296 { PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 },
297 { PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f },
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/linux/drivers/net/ethernet/dec/tulip/
H A Dpnic.c23 u32 phy_reg = ioread32(ioaddr + 0xB8); in pnic_do_nway() local
26 if (phy_reg & 0x78000000) { /* Ignore baseT4 */ in pnic_do_nway()
27 if (phy_reg & 0x20000000) dev->if_port = 5; in pnic_do_nway()
28 else if (phy_reg & 0x40000000) dev->if_port = 3; in pnic_do_nway()
29 else if (phy_reg & 0x10000000) dev->if_port = 4; in pnic_do_nway()
30 else if (phy_reg & 0x08000000) dev->if_port = 0; in pnic_do_nway()
36 if (phy_reg & 0x30000000) { in pnic_do_nway()
42 phy_reg, medianame[dev->if_port]); in pnic_do_nway()
56 int phy_reg = ioread32(ioaddr + 0xB8); in pnic_lnk_change() local
60 phy_reg, csr5); in pnic_lnk_change()
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/linux/drivers/clk/hisilicon/
H A Dclk-hix5hd2.c139 u32 phy_reg; member
151 void __iomem *phy_reg; member
180 val = readl_relaxed(clk->phy_reg); in clk_ether_prepare()
183 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
188 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
193 writel_relaxed(val, clk->phy_reg); in clk_ether_prepare()
223 val = readl_relaxed(clk->phy_reg); in clk_complex_enable()
226 writel_relaxed(val, clk->phy_reg); in clk_complex_enable()
241 val = readl_relaxed(clk->phy_reg); in clk_complex_disable()
244 writel_relaxed(val, clk->phy_reg); in clk_complex_disable()
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/linux/drivers/usb/phy/
H A Dphy-am335x-control.c13 void __iomem *phy_reg; member
84 val = readl(usb_ctrl->phy_reg + reg); in am335x_phy_power()
98 writel(val, usb_ctrl->phy_reg + reg); in am335x_phy_power()
168 ctrl_usb->phy_reg = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl"); in am335x_control_usb_probe()
169 if (IS_ERR(ctrl_usb->phy_reg)) in am335x_control_usb_probe()
170 return PTR_ERR(ctrl_usb->phy_reg); in am335x_control_usb_probe()
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-isys-mcd-phy.c104 struct phy_reg { struct
109 static const struct phy_reg common_init_regs[] = { argument
129 static const struct phy_reg x1_port0_config_regs[] = {
153 static const struct phy_reg x1_port1_config_regs[] = {
177 static const struct phy_reg x1_port2_config_regs[] = {
201 static const struct phy_reg x1_port3_config_regs[] = {
225 static const struct phy_reg x2_port0_config_regs[] = {
259 static const struct phy_reg x2_port1_config_regs[] = {
293 static const struct phy_reg x2_port2_config_regs[] = {
326 static const struct phy_reg x2_port3_config_regs[] = {
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/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_mdio.c188 int phy_reg, u32 opcode) in mlxbf_gige_mdio_create_cmd() argument
194 gw_reg |= ((phy_reg << mdio_gw->devad.shift) & in mlxbf_gige_mdio_create_cmd()
208 static int mlxbf_gige_mdio_read(struct mii_bus *bus, int phy_add, int phy_reg) in mlxbf_gige_mdio_read() argument
216 cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, 0, phy_add, phy_reg, in mlxbf_gige_mdio_read()
241 int phy_reg, u16 val) in mlxbf_gige_mdio_write() argument
249 cmd = mlxbf_gige_mdio_create_cmd(priv->mdio_gw, val, phy_add, phy_reg, in mlxbf_gige_mdio_write()
/linux/drivers/net/dsa/
H A Dlan9303_mdio.c18 #define PHY_REG(x) (((x) >> 1) & 0x1f) macro
27 mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val); in lan9303_mdio_real_write()
45 return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg)); in lan9303_mdio_real_read()
/linux/drivers/net/phy/
H A Dphy_device.c878 int phy_reg; in get_phy_c45_devs_in_pkg() local
880 phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS2); in get_phy_c45_devs_in_pkg()
881 if (phy_reg < 0) in get_phy_c45_devs_in_pkg()
883 *devices_in_package = phy_reg << 16; in get_phy_c45_devs_in_pkg()
885 phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS1); in get_phy_c45_devs_in_pkg()
886 if (phy_reg < 0) in get_phy_c45_devs_in_pkg()
888 *devices_in_package |= phy_reg; in get_phy_c45_devs_in_pkg()
911 int i, ret, phy_reg; in get_phy_c45_ids() local
936 phy_reg = get_phy_c45_devs_in_pkg(bus, addr, i, &devs_in_pkg); in get_phy_c45_ids()
937 if (phy_reg < 0) in get_phy_c45_ids()
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/linux/drivers/net/usb/
H A Dasix_devices.c72 int phy_reg; in asix_get_phyid() local
78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); in asix_get_phyid()
79 if (phy_reg < 0) in asix_get_phyid()
81 if (phy_reg != 0 && phy_reg != 0xFFFF) in asix_get_phyid()
86 if (phy_reg <= 0 || phy_reg == 0xFFFF) in asix_get_phyid()
89 phy_id = (phy_reg & 0xffff) << 16; in asix_get_phyid()
91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); in asix_get_phyid()
92 if (phy_reg < 0) in asix_get_phyid()
95 phy_id |= (phy_reg & 0xffff); in asix_get_phyid()
/linux/drivers/net/ieee802154/
H A Dmcr20a.c1082 unsigned int phy_reg = 0; in mcr20a_phy_init() local
1164 phy_reg = (u8)(((index & DAR_SRC_CTRL_INDEX) << in mcr20a_phy_init()
1168 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, phy_reg); in mcr20a_phy_init()
1171 phy_reg = 0; in mcr20a_phy_init()
1175 ret = regmap_read(lp->regmap_iar, IAR_DUAL_PAN_CTRL, &phy_reg); in mcr20a_phy_init()
1180 phy_reg &= ~IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK; in mcr20a_phy_init()
1183 phy_reg |= MCR20A_PHY_INDIRECT_QUEUE_SIZE << in mcr20a_phy_init()
1185 ret = regmap_write(lp->regmap_iar, IAR_DUAL_PAN_CTRL, phy_reg); in mcr20a_phy_init()
/linux/drivers/pinctrl/ti/
H A Dpinctrl-ti-iodelay.c756 u32 phy_reg; in ti_iodelay_alloc_pins() local
769 phy_reg = r->reg_start_offset + base_phy; in ti_iodelay_alloc_pins()
771 for (i = 0; i < nr_pins; i++, phy_reg += 4) { in ti_iodelay_alloc_pins()
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c327 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, in _mtk_mdio_write_c22() argument
339 PHY_IAC_REG(phy_reg) | in _mtk_mdio_write_c22()
352 u32 devad, u32 phy_reg, u32 write_data) in _mtk_mdio_write_c45() argument
365 PHY_IAC_DATA(phy_reg), in _mtk_mdio_write_c45()
387 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) in _mtk_mdio_read_c22() argument
398 PHY_IAC_REG(phy_reg) | in _mtk_mdio_read_c22()
410 u32 devad, u32 phy_reg) in _mtk_mdio_read_c45() argument
423 PHY_IAC_DATA(phy_reg), in _mtk_mdio_read_c45()
445 int phy_reg, u16 val) in mtk_mdio_write_c22() argument
449 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, va in mtk_mdio_write_c22()
453 mtk_mdio_write_c45(struct mii_bus * bus,int phy_addr,int devad,int phy_reg,u16 val) mtk_mdio_write_c45() argument
460 mtk_mdio_read_c22(struct mii_bus * bus,int phy_addr,int phy_reg) mtk_mdio_read_c22() argument
468 mtk_mdio_read_c45(struct mii_bus * bus,int phy_addr,int devad,int phy_reg) mtk_mdio_read_c45() argument
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/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h2912 #define PHY_REG(page, reg) \ macro
2916 PHY_REG(769, 17) /* Port General Configuration */
2918 PHY_REG(769, 25) /* Rate Adapter Control Register */
2921 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2923 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2925 PHY_REG(770, 18) /* KMRN Inband Control Register */
2927 PHY_REG(770, 19) /* KMRN Diagnostic register */
2930 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2933 PHY_REG(776, 18) /* Voltage regulator control register */
2938 PHY_REG(776, 19) /* IGP3 Capability Register */
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A Digb_ethtool.c1755 u16 phy_reg; in igb_loopback_cleanup() local
1780 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); in igb_loopback_cleanup()
1781 if (phy_reg & MII_CR_LOOPBACK) { in igb_loopback_cleanup()
1782 phy_reg &= ~MII_CR_LOOPBACK; in igb_loopback_cleanup()
1783 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); in igb_loopback_cleanup()
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h230 #define PHY_REG 0x02F3 macro
H A Dphy.c882 /* 1. Read PHY_REG.TXT BB INIT!! */ in _rtl92s_phy_bb_config_parafile()

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