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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Damlogic,meson-g12a-usb-ctrl.yaml114 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
133 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
153 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
168 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
187 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
214 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-388-clearfog-base.dts33 phy = <&phy1>;
41 line-name = "phy1-reset";
47 phy1: ethernet-phy@1 { label
59 /* phy1 reset */
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,sm8450-dispcc.yaml32 - description: Byte clock from DSI PHY1
33 - description: Pixel clock from DSI PHY1
36 - description: Link clock from DP PHY1
37 - description: VCO DIV clock from DP PHY1
H A Dqcom,sm8550-dispcc.yaml37 - description: Byte clock from DSI PHY1
38 - description: Pixel clock from DSI PHY1
41 - description: Link clock from DP PHY1
42 - description: VCO DIV clock from DP PHY1
H A Dqcom,gcc-msm8953.yaml29 - description: Byte clock from DSI PHY1
30 - description: Pixel clock from DSI PHY1
H A Dqcom,gcc-msm8976.yaml31 - description: Pixel clock from DSI PHY1
32 - description: Byte clock from DSI PHY1
H A Dqcom,sm7150-dispcc.yaml32 - description: Byte clock from MDSS DSI PHY1
33 - description: Pixel clock from MDSS DSI PHY1
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr8a7743-sk-rzg1m.dts51 phy1_pins: phy1 {
68 phy-handle = <&phy1>;
72 phy1: ethernet-phy@1 { label
H A Dr8a7745-sk-rzg1e.dts46 phy1_pins: phy1 {
63 phy-handle = <&phy1>;
67 phy1: ethernet-phy@1 { label
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110-pine64-star64.dts24 phy-handle = <&phy1>;
36 phy1: ethernet-phy@1 { label
56 &phy1 {
H A Djh7110-starfive-visionfive-2.dtsi17 phy-handle = <&phy1>;
26 phy1: ethernet-phy@1 { label
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-usb.dtsi29 phy-names = "phy0", "phy1";
39 phy-names = "phy0", "phy1";
63 phy-names = "phy0", "phy1", "phy2";
/freebsd/sys/contrib/device-tree/src/arm/axis/
H A Dartpec6-devboard.dts51 phy-handle = <&phy1>;
58 phy1: phy@0 { label
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a-kontron-sl28-var4.dts22 phy1: ethernet-phy@4 { label
44 phy-handle = <&phy1>;
H A Dfsl-ls1028a-kontron-sl28-var2.dts21 phy1: ethernet-phy@4 { label
67 phy-handle = <&phy1>;
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun7i-a20-icnova-a20.dtsi16 phy-handle = <&phy1>;
32 phy1: ethernet-phy@1 { label
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dqcom,ethqos.txt53 phy-handle = <&phy1>;
60 phy1: phy@4 {
H A Dsocionext,synquacer-netsec.yaml62 phy-handle = <&phy1>;
67 phy1: ethernet-phy@1 {
H A Dsocionext-netsec.txt47 phy-handle = <&phy1>;
52 phy1: ethernet-phy@1 {
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-stp-xway.txt24 - lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.
39 lantiq,phy1 = <0x7>;
/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A Dmpfs-polarberry.dts45 phy-handle = <&phy1>;
48 phy1: ethernet-phy@5 {
55 phy1: ethernet-phy@5 { global() label
/freebsd/sys/contrib/device-tree/src/arm/intel/ixp/
H A Dintel-ixp42x-ixdp425.dts57 phy1: ethernet-phy@1 { label
69 phy-handle = <&phy1>;
H A Dintel-ixp43x-kixrp435.dts43 phy-handle = <&phy1>;
49 phy1: ethernet-phy@1 { label
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhisi-x5hd2-dkb.dts69 phy-handle = <&phy1>;
75 phy1: ethernet-phy@1 { label
/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k2000-ref.dts81 phy-handle = <&phy1>;
86 phy1: ethernet-phy@1 { label

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