Home
last modified time | relevance | path

Searched +full:phy +full:- +full:pma (Results 1 – 25 of 25) sorted by relevance

/linux/Documentation/devicetree/bindings/net/pcs/
H A Dsnps,dw-xpcs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
17 optionally synthesized with a vendor-specific interface connected to
18 Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in
19 general it can be used to communicate with any compatible PHY.
28 - description: Synopsys DesignWare XPCS with none or unknown PMA
29 const: snps,dw-xpcs
[all …]
/linux/rust/kernel/net/phy/
H A Dreg.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! PHY register interfaces.
7 //! This module provides support for accessing PHY registers in the
21 /// Accesses PHY registers.
24 /// C22 and C45 PHY registers.
32 /// // read C45 PMA/PMD control 1 register
37 /// dev.genphy_read_status::<phy::C22>();
40 /// dev.genphy_read_status::<phy::C45>();
44 /// Reads a PHY register.
45 fn read(&self, dev: &mut Device) -> Result<u16>; in read()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
[all …]
/linux/drivers/net/ethernet/sfc/falcon/
H A Dqt202x_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2012 Solarflare Communications Inc.
15 #include "phy.h"
27 /* Quake-specific MDIO registers */
85 ((1 << PCS_FW_HEARTB_WIDTH) - 1)); in qt2025c_wait_heartbeat()
92 * PHY's on-board EEPROM so it cannot load firmware */ in qt2025c_wait_heartbeat()
93 netif_err(efx, hw, efx->net_dev, in qt2025c_wait_heartbeat()
97 return -ETIMEDOUT; in qt2025c_wait_heartbeat()
116 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= in qt2025c_wait_fw_status_good()
120 return -ETIMEDOUT; in qt2025c_wait_fw_status_good()
[all …]
H A Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
16 #include "phy.h"
30 * Compile-time config
35 /* Total length of time we'll wait for the PHY to come out of reset (ms) */
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
69 /* Lane power-down */
108 /* Lane power-down */
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
[all …]
H A Dcdns,dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pratyush Yadav <pratyush@kernel.org>
15 - cdns,dphy
16 - ti,j721e-dphy
23 - description: PMA state machine clock
24 - description: PLL reference clock
26 clock-names:
[all …]
H A Dsamsung,usb3-drd-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16 compatible PHYs, the second cell in the PHY specifier identifies the
[all …]
/linux/drivers/net/pcs/
H A Dpcs-xpcs.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pcs/pcs-xpcs.h>
13 #include <linux/phy.h>
17 #include "pcs-xpcs.h"
128 for (compat = xpcs->desc->compat; compat->supported; compat++) in xpcs_find_compat()
129 if (compat->interface == interface) in xpcs_find_compat()
137 return &xpcs->pcs; in xpcs_to_phylink_pcs()
147 return -ENODEV; in xpcs_get_an_mode()
149 return compat->an_mode; in xpcs_get_an_mode()
158 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) in __xpcs_linkmode_supported()
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
24 The AUX and PMA registers are not part of this range, they are instead
[all …]
/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos5 SoC series USB DRD PHY driver
5 * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
19 #include <linux/phy/phy.h>
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
27 /* Exynos USB PHY registers */
37 /* Exynos5: USB 3.0 DRD PHY registers */
116 /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
135 /* Exynos850: USB DRD PHY registers */
149 * On versions without SS ports (like E850), bit 3 is for the 2.0 phy (HS),
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dael1002.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
62 /* PHY module I2C device address */
68 /* PHY transceiver type */
84 static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) in set_phy_regs() argument
88 for (err = 0; rv->mmd_addr && !err; rv++) { in set_phy_regs()
89 if (rv->clear_bits == 0xffff) in set_phy_regs()
90 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, in set_phy_regs()
91 rv->set_bits); in set_phy_regs()
[all …]
/linux/drivers/scsi/bfa/
H A Dbfa_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */
102 * All numerical fields are in big-endian format.
125 BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if persists,
129 BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */
132 BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */
148 BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
30 arm-pmu {
31 compatible = "arm,cortex-a57-pmu";
36 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
42 compatible = "fixed-clock";
[all …]
H A Dexynosautov9.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov9.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,boot-mode.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a76-pmu";
[all …]
/linux/drivers/net/phy/
H A Dmarvell-88q2xxx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell 88Q2XXX automotive 100BASE-T1/1000BASE-T1 PHY driver
7 * Copyright (C) 2024 Liebherr-Electronics and Drives GmbH
11 #include <linux/phy.h>
202 for (; len; vals++, len--) { in mv88q2xxx_write_mmd_vals()
203 ret = phy_write_mmd(phydev, vals->devad, vals->regnum, in mv88q2xxx_write_mmd_vals()
204 vals->val); in mv88q2xxx_write_mmd_vals()
218 if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed == SPEED_1000) { in mv88q2xxx_soft_reset()
241 if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed == SPEED_1000) in mv88q2xxx_soft_reset()
252 /* Read vendor specific Auto-Negotiation status register to get local in mv88q2xxx_read_link_gbit()
[all …]
/linux/drivers/net/ethernet/atheros/alx/
H A Dhw.c58 return -ETIMEDOUT; in alx_wait_mdio_idle()
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_read_phy_core()
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_write_phy_core()
175 spin_lock(&hw->mdio_lock); in alx_read_phy_reg()
177 spin_unlock(&hw->mdio_lock); in alx_read_phy_reg()
186 spin_lock(&hw->mdio_lock); in alx_write_phy_reg()
188 spin_unlock(&hw->mdio_lock); in alx_write_phy_reg()
197 spin_lock(&hw->mdio_lock); in alx_read_phy_ext()
199 spin_unlock(&hw->mdio_lock); in alx_read_phy_ext()
208 spin_lock(&hw->mdio_lock); in alx_write_phy_ext()
[all …]
/linux/arch/arm64/boot/dts/tesla/
H A Dfsd.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
[all …]
H A Defx_common.c1 // SPDX-License-Identifier: GPL-2.0-only
37 * On Falcon-based NICs, this will:
38 * - Check the on-board hardware monitor;
39 * - Poll the link state and reconfigure the hardware as necessary.
40 * On Siena-based NICs for power systems with EEH support, this will give EEH a
95 [LOOPBACK_PMAPMD] = "PMA/PMD",
108 * queued onto this work queue. This is not a per-nic work queue, because
118 return -ENOMEM; in efx_siena_create_reset_workqueue()
126 queue_work(reset_workqueue, &efx->reset_work); in efx_siena_queue_reset_work()
131 cancel_work_sync(&efx->reset_work); in efx_siena_flush_reset_workqueue()
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * http://www.t10.org/lists/asc-num.txt [most recent: 20200817]
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
51 SENSE_CODE(0x0409, "Logical unit not ready, self-test in progress")
87 SENSE_CODE(0x0801, "Logical unit communication time-out")
89 SENSE_CODE(0x0803, "Logical unit communication CRC error (Ultra-DMA/32)")
102 SENSE_CODE(0x0B01, "Warning - specified temperature exceeded")
103 SENSE_CODE(0x0B02, "Warning - enclosure degraded")
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
[all …]
/linux/drivers/net/ethernet/sun/
H A Dniu.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
55 #define niu_next_page(p) container_of(p, union niu_page, page)->next
91 #define nr64(reg) readq(np->regs + (reg))
92 #define nw64(reg, val) writeq((val), np->regs + (reg))
94 #define nr64_mac(reg) readq(np->mac_regs + (reg))
95 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
97 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
98 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
100 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
44 #include <linux/phy.h>
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
94 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
96 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
98 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
[all …]