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/linux/drivers/phy/
H A Dphy-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-core.c -- Generic Phy framework.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
15 #include <linux/device.h>
18 #include <linux/phy/phy.h>
23 static void phy_release(struct device *dev);
25 .name = "phy",
35 static void devm_phy_release(struct device *dev, void *res) in devm_phy_release()
37 struct phy *phy = *(struct phy **)res; in devm_phy_release() local
39 phy_put(dev, phy); in devm_phy_release()
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/linux/Documentation/translations/zh_CN/driver-api/phy/
H A Dphy.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../../disclaimer-zh_CN.rst
4 :Original: Documentation/driver-api/phy/phy.rst
16 本文档解释了 PHY 的通用框架和提供的API，以及使用方法。
21 *PHY* 是物理层的缩写，它被用来把设备连接到一个物理媒介，例如USB控制器
22 有一个提供序列化、反序列化、编码、解码和负责获取所需的数据传输速率的 PHY。
23 注意，有些USB控制器内嵌了 PHY 的功能，其它的则使用了一个外置的PHY，此外
24 使用 PHY 的设备还有无线网、以太网、SATA等（控制器）。
26 创建这个框架的目的是将遍布 Linux 内核的 PHY 驱动程序融入到 drivers/phy，
29 该框架仅适用于使用外部 PHY（PHY 功能未嵌入控制器内）的设备。
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/linux/drivers/scsi/hisi_sas/
H A Dhisi_sas_main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 ((!dev) || (dev->dev_type == SAS_PHY_UNUSED))
23 static int hisi_sas_softreset_ata_disk(struct domain_device *device);
27 struct domain_device *device);
28 static void hisi_sas_dev_gone(struct domain_device *device);
39 switch (qc->tf.protocol) { in hisi_sas_get_ata_protocol_from_tf()
56 struct host_to_dev_fis *fis = &task->ata_task.fis; in hisi_sas_get_ata_protocol()
57 struct ata_queued_cmd *qc = task->uldd_task; in hisi_sas_get_ata_protocol()
58 int direction = task->data_dir; in hisi_sas_get_ata_protocol()
60 switch (fis->command) { in hisi_sas_get_ata_protocol()
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/linux/drivers/usb/phy/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * phy.c -- USB phy handling
5 * Copyright (C) 2004-2013 Texas Instruments
10 #include <linux/device.h>
15 #include <linux/usb/phy.h>
33 struct usb_phy *phy; member
54 struct usb_phy *phy = NULL; in __usb_find_phy() local
56 list_for_each_entry(phy, list, head) { in __usb_find_phy()
57 if (phy->type != type) in __usb_find_phy()
60 return phy; in __usb_find_phy()
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/linux/drivers/usb/core/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
4 * multiple (actual) PHY devices. This is comes handy when initializing
10 #include <linux/device.h>
12 #include <linux/phy/phy.h>
15 #include "phy.h"
18 struct phy *phy; member
22 /* Allocate the roothub_entry by specific name of phy */
23 static int usb_phy_roothub_add_phy_by_name(struct device *dev, const char *name, in usb_phy_roothub_add_phy_by_name()
27 struct phy *phy; in usb_phy_roothub_add_phy_by_name() local
29 phy = devm_of_phy_get(dev, dev->of_node, name); in usb_phy_roothub_add_phy_by_name()
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/linux/drivers/dma/
H A Dmmp_pdma.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
15 #include <linux/device.h>
37 #define DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
39 #define DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
40 #define DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
69 #define DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
76 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
86 * The following 32-bit words are only used in the 64-bit, ie.
91 u32 ddadrh; /* High 32-bit of DDADR */
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H A Dpxa_dma.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
16 #include <linux/device.h>
22 #include <linux/dma/pxa-dma.h>
25 #include "virt-dma.h"
36 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
38 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
39 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
64 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
71 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
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/linux/drivers/scsi/smartpqi/
H A Dsmartpqi_sas_transport.c1 // SPDX-License-Identifier: GPL-2.0
3 * driver for Microchip PQI-based storage controllers
4 * Copyright (c) 2019-2023 Microchip Technology Inc. and its subsidiaries
5 * Copyright (c) 2016-2018 Microsemi Corporation
6 * Copyright (c) 2016 PMC-Sierra, Inc.
13 #include <linux/bsg-lib.h>
23 struct sas_phy *phy; in pqi_alloc_sas_phy() local
29 phy = sas_phy_alloc(pqi_sas_port->parent_node->parent_dev, in pqi_alloc_sas_phy()
30 pqi_sas_port->next_phy_index); in pqi_alloc_sas_phy()
31 if (!phy) { in pqi_alloc_sas_phy()
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-phydev1 What: /sys/class/mdio_bus/<bus>/<device>/attached_dev
6 Symbolic link to the network device this PHY device is
9 What: /sys/class/mdio_bus/<bus>/<device>/phy_has_fixups
14 This attribute contains the boolean value whether a given PHY
15 device has had any "fixup" workaround running on it, encoded as
17 PHY configurations.
19 What: /sys/class/mdio_bus/<bus>/<device>/phy_id
24 This attribute contains the 32-bit PHY Identifier as reported
25 by the device during bus enumeration, encoded in hexadecimal.
26 This ID is used to match the device with the appropriate
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/linux/drivers/scsi/mpi3mr/
H A Dmpi3mr_transport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
15 * mpi3mr_post_transport_req - Issue transport requests and wait
33 * Return: 0 on success, non-zero on failure.
41 mutex_lock(&mrioc->transport_cmds.mutex); in mpi3mr_post_transport_req()
42 if (mrioc->transport_cmds.state & MPI3MR_CMD_PENDING) { in mpi3mr_post_transport_req()
43 retval = -1; in mpi3mr_post_transport_req()
45 mutex_unlock(&mrioc->transport_cmds.mutex); in mpi3mr_post_transport_req()
48 mrioc->transport_cmds.state = MPI3MR_CMD_PENDING; in mpi3mr_post_transport_req()
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/linux/drivers/phy/broadcom/
H A Dphy-bcm-cygnus-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
24 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
25 * @core: pointer to the Cygnus PCIe PHY core control
26 * @id: internal ID to identify the Cygnus PCIe PHY
27 * @phy: pointer to the kernel PHY device
32 struct phy *phy; member
36 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
37 * @dev: pointer to device
40 * @phys: pointer to Cygnus PHY device
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H A Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
43 * @index: PHY index
44 * @phy: pointer to the kernel PHY device
49 struct phy *phy; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
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/linux/rust/kernel/net/
H A Dphy.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! Network PHY device.
7 //! C headers: [`include/linux/phy.h`](srctree/include/linux/phy.h).
14 /// PHY state machine states.
18 /// Some of PHY drivers access to the state of PHY's software state machine.
20 /// [`enum phy_state`]: srctree/include/linux/phy.h
23 /// PHY device and driver are not ready for anything.
25 /// PHY is ready to send and receive packets.
27 /// PHY is up, but no polling or interrupts are done.
29 /// PHY is up, but is in an error state.
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/linux/drivers/phy/hisilicon/
H A Dphy-hi3670-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe phy driver for Kirin 970
22 #include <linux/device.h>
28 #include <linux/phy/phy.h>
48 /* PCIe PHY registers */
157 struct device *dev;
172 static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val, in hi3670_apb_phy_writel() argument
175 writel(val, phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_writel()
178 static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg) in hi3670_apb_phy_readl() argument
180 return readl(phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_readl()
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-bindings.txt1 This document explains only the device tree data binding. For general
2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
19 phys: phy {
24 #phy-cells = <1>;
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H A Dmarvell,armada-cp110-utmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell Armada CP110/CP115 UTMI PHY
11 - Konstantin Porotchkin <kostap@marvell.com>
14 On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device
17 The USB device controller can only be connected to a single UTMI PHY port
18 0.H----- USB HOST0
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H A Dti,da830-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,da830-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI DA8xx/OMAP-L1xx/AM18xx USB PHY
10 - David Lechner <david@lechnology.com>
13 This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
16 It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
22 - const: ti,da830-usb-phy
24 '#phy-cells':
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/linux/include/linux/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
26 #include <linux/device-id/mdio.h>
56 * Set phydev->irq to PHY_POLL if interrupts are not supported,
57 * or not desired for this PHY. Set to PHY_MAC_INTERRUPT if
60 #define PHY_POLL -1
61 #define PHY_MAC_INTERRUPT -2
70 * enum phy_interface_t - Interface Mode definitions
72 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
73 * @PHY_INTERFACE_MODE_INTERNAL: No interface, MAC and PHY combined
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/linux/drivers/net/phy/
H A Dphy_device.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Also contains generic PHY driver
29 #include <linux/phy.h>
34 #include <linux/pse-pd/pse.h>
45 #include "phylib-internal.h"
46 #include "phy-caps.h"
48 MODULE_DESCRIPTION("PHY library");
63 .name = "Generic Clause 45 PHY",
212 put_device(&phydev->mdio.dev); in phy_device_free()
224 static void phy_device_release(struct device *dev) in phy_device_release()
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/linux/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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H A Dcpsw.txt1 TI SoC Ethernet Switch Controller Device Tree Bindings
2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
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/linux/drivers/phy/ralink/
H A Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/phy/phy.h>
56 struct phy *phy; member
61 static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg) in u2_phy_w32() argument
63 writel(val, phy->base + reg); in u2_phy_w32()
66 static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg) in u2_phy_r32() argument
68 return readl(phy->base + reg); in u2_phy_r32()
71 static void ralink_usb_phy_init(struct ralink_usb_phy *phy) in ralink_usb_phy_init() argument
73 u2_phy_r32(phy, OFS_U2_PHY_AC2); in ralink_usb_phy_init()
74 u2_phy_r32(phy, OFS_U2_PHY_ACR0); in ralink_usb_phy_init()
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H A Dphy-mt7621-pci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Mediatek MT7621 PCI PHY Driver
7 #include <dt-bindings/phy/phy.h>
13 #include <linux/phy/phy.h>
66 * struct mt7621_pci_phy - Mt7621 Pcie PHY core
67 * @dev: pointer to device
69 * @phy: pointer to the kernel PHY device
72 * @has_dual_port: if the phy has dual ports.
77 struct device *dev;
79 struct phy *phy; member
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/linux/drivers/scsi/pm8001/
H A Dpm8001_sas.c2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
18 * 3. Neither the names of the above-listed copyright holders nor the names
46 * pm8001_find_tag - from sas task to find out tag that belongs to this task
52 if (task->lldd_task) { in pm8001_find_tag()
54 ccb = task->lldd_task; in pm8001_find_tag()
55 *tag = ccb->ccb_tag; in pm8001_find_tag()
62 * pm8001_tag_free - free the no more needed tag
68 void *bitmap = pm8001_ha->rsvd_tags; in pm8001_tag_free()
74 spin_lock_irqsave(&pm8001_ha->bitmap_lock, flags); in pm8001_tag_free()
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/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
13 #include <linux/phy/phy.h>
20 #include <linux/phy/omap_control_phy.h>
168 struct device *dev;
169 struct device *control_dev;
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
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