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/freebsd/share/doc/smm/03.fsck/
H A D4.t37 Each file system pass invokes a different Phase of the
78 .I Phase
83 in more than one Phase
391 Phase 1 \- Check Blocks and Sizes
393 This phase concerns itself with
401 All errors in this phase except
417 This will always invoke the UNALLOCATED error condition in Phase 2
471 error condition in Phase 1 (see next paragraph) if
475 error condition in Phase 2 and Phase 4.
512 error condition in Phase 1 if
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H A D0.t136 4.3. Phase 1 - Check Blocks and Sizes
137 4.4. Phase 1b - Rescan for more Dups
138 4.5. Phase 2 - Check Pathnames
139 4.6. Phase 3 - Check Connectivity
140 4.7. Phase 4 - Check Reference Counts
141 4.8. Phase 5 - Check Cyl groups
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsamsung,exynos-dw-mshc.yaml61 - description: CIU clock phase shift value for tx mode
64 - description: CIU clock phase shift value for rx mode
68 The value of CUI clock phase shift value in transmit mode and CIU clock
69 phase shift value in receive mode for double data rate mode operation.
75 - description: CIU clock phase shift value for tx mode
78 - description: CIU clock phase shift value for rx mode
82 The value of CIU TX and RX clock phase shift value for HS400 mode
85 - valid value for tx phase shift and rx phase shift is 0 to 7.
86 - when CIU clock divider value is set to 3, all possible 8 phase shif
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H A Dexynos-dw-mshc.txt32 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
33 in transmit mode and CIU clock phase shift value in receive mode for single
37 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
38 in transmit mode and CIU clock phase shift value in receive mode for double
41 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
47 - First Cell: CIU clock phase shift value for tx mode.
48 - Second Cell: CIU clock phase shift value for rx mode.
51 - valid value for tx phase shift and rx phase shift is 0 to 7.
52 - when CIU clock divider value is set to 3, all possible 8 phase shift
55 phase shift clocks should be 0.
/freebsd/contrib/wpa/hostapd/
H A Dhostapd.eap_user12 # [2] flag in the end of the line can be used to mark users for tunneled phase
14 # identity can be used in the unencrypted phase 1 and the real user identity
15 # is transmitted only within the encrypted tunnel in phase 2. If non-anonymous
16 # access is needed, two user entries is needed, one for phase 1 and another
17 # with the same username for phase 2.
23 # EAP-PEAP, EAP-TTLS, and EAP-FAST require Phase 2 configuration.
26 # this are to set anonymous phase 1 identity for EAP-PEAP and EAP-TTLS and to
28 # first matching entry is selected, so * should be used as the last phase 1
34 # is only allowed for phase 1 identities.
41 # version based on the Phase 1 identity. Without this flag, the EAP
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/freebsd/lib/libc/powerpc64/string/
H A Dbcopy.S196 /* set up multi-phase copy parameters */
213 std %r7, -32(%r1) /* bytes to copy in phase 1 */
214 std %r10, -40(%r1) /* BLOCKS to copy in phase 2 */
215 std %r9, -48(%r1) /* bytes to copy in phase 3 */
218 li %r5, BLOCK_SIZE /* increment for phase 2 */
220 /* op offsets for phase 2 */
233 std %r9, -32(%r1) /* bytes to copy in phase 1 */
234 std %r10, -40(%r1) /* BLOCKS to copy in phase 2 */
235 std %r7, -48(%r1) /* bytes to copy in phase 3 */
239 li %r5, -BLOCK_SIZE /* increment for phase 2 */
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/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Drealtek,otto-wdt.yaml15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
20 During this phase, pinging the WDT has no effect, and a reset is
/freebsd/contrib/llvm-project/libunwind/src/
H A DUnwind-sjlj.c185 // walk each frame until we reach where search phase said to stop in unwind_phase2()
207 // in phase 1 in unwind_phase2()
218 // phase 1 said we would stop at this frame, but we did not... in unwind_phase2()
244 // clean up phase did not resume at the frame that the search phase said it in unwind_phase2()
253 // walk each frame until we reach where search phase said to stop in unwind_phase2_forced()
328 // clean up phase did not resume at the frame that the search phase said it in unwind_phase2_forced()
345 // phase 1: the search phase in _Unwind_SjLj_RaiseException()
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H A DUnwindLevel1.c207 // Walk each frame until we reach where search phase said to stop. in unwind_phase2()
279 // Tell personality this was the frame it marked in phase 1. in unwind_phase2()
292 // Phase 1 said we would stop at this frame, but we did not... in unwind_phase2()
325 // Clean up phase did not resume at the frame that the search phase in unwind_phase2()
343 // Walk each frame until we reach where search phase said to stop in unwind_phase2_forced()
438 // Clean up phase did not resume at the frame that the search phase said it in unwind_phase2_forced()
458 // phase 1: the search phase in _Unwind_RaiseException()
463 // phase 2: the clean up phase in _Unwind_RaiseException()
522 /// Called by personality handler during phase 2 to get LSDA for current frame.
544 /// Called by personality handler during phase 2 to find the start of the
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Drenesas,rz-mtu3.yaml31 - Up to 12-phase PWM output in combination with synchronous operation
36 - Phase counting mode can be specified independently
37 - 32-bit phase counting mode can be specified for interlocked operation
57 - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
75 There are two phase counting modes. 16-bit phase counting mode in which
76 MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
79 In phase counting mode, the phase difference between two external input
83 count0 - MTU1 16-bit phase countin
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/freebsd/sys/contrib/device-tree/Bindings/iio/proximity/
H A Dsemtech,sx9324.yaml45 Value indicates how each CS pin is used during phase 0.
59 description: Same as ph0-pin for phase 1.
67 description: Same as ph0-pin for phase 2.
75 description: Same as ph0-pin for phase 3.
86 Capacitance measurement resolution. For phase 0 and 1.
94 Capacitance measurement resolution. For phase 2 and 3
102 Phase used for start-up proximity detection.
103 It is used when we enable a phase to remove static offset and measure
112 PROXRAW filter strength for phase 0 and 1. A value of 0 represents off,
121 Same as proxraw-strength01, for phase
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/freebsd/sys/dev/qat/qat_api/include/lac/
H A Dcpa_cy_dh.h70 * Diffie-Hellman Phase 1 Key Generation Data.
107 * phase 2 Diffie-Hellman operation.*/
113 * Diffie-Hellman Phase 2 Secret Key Generation Data.
135 * This SHOULD be same prime number as was used in the phase 1 key
161 /**< Total number of successful Diffie-Hellman phase 1 key
164 /**< Total number of Diffie-Hellman phase 1 key generation requests
167 /**< Total number of Diffie-Hellman phase 1 key generation operations
170 /**< Total number of Diffie-Hellman phase 1 key generation operations
173 /**< Total number of successful Diffie-Hellman phase 2 key
176 /**< Total number of Diffie-Hellman phase 2 key generation requests
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Daxp20x.txt127 DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
128 DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
130 DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
131 DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
154 DCDCA : DC-DC buck : vina-supply : poly-phase capable
155 DCDCB : DC-DC buck : vinb-supply : poly-phase capable
156 DCDCC : DC-DC buck : vinc-supply : poly-phase capable
157 DCDCD : DC-DC buck : vind-supply : poly-phase capable
158 DCDCE : DC-DC buck : vine-supply : poly-phase capable
171 Additionally, the AXP806 DC-DC regulators support poly-phase arrangements
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/freebsd/sys/contrib/device-tree/Bindings/
H A Dtrivial-devices.yaml132 # Infineon Multi-phase Digital VR Controller xdpe11280
134 # Infineon Multi-phase Digital VR Controller xdpe12254
136 # Infineon Multi-phase Digital VR Controller xdpe12284
138 # Infineon Multi-phase Digital VR Controller xdpe15284
140 # Infineon Multi-phase Digital VR Controller xdpe152c4
274 # Monolithic Power Systems Inc. multi-phase controller mp2856
276 # Monolithic Power Systems Inc. multi-phase controller mp2857
278 # Monolithic Power Systems Inc. multi-phase controller mp2888
280 # Monolithic Power Systems Inc. multi-phase controller mp2891
282 # Monolithic Power Systems Inc. multi-phase controller mp2971
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/freebsd/sys/contrib/openzfs/module/zstd/lib/compress/
H A Dzstd_cwksp.h142 ZSTD_cwksp_alloc_phase_e phase; member
189 ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase) { in ZSTD_cwksp_internal_advance_phase() argument
190 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
191 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
192 if (ws->phase < ZSTD_cwksp_alloc_buffers && in ZSTD_cwksp_internal_advance_phase()
193 phase >= ZSTD_cwksp_alloc_buffers) { in ZSTD_cwksp_internal_advance_phase()
196 if (ws->phase < ZSTD_cwksp_alloc_aligned && in ZSTD_cwksp_internal_advance_phase()
197 phase >= ZSTD_cwksp_alloc_aligned) { in ZSTD_cwksp_internal_advance_phase()
210 ws->phase = phase; in ZSTD_cwksp_internal_advance_phase()
225 ZSTD_cwksp* ws, size_t bytes, ZSTD_cwksp_alloc_phase_e phase) { in ZSTD_cwksp_reserve_internal() argument
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/freebsd/sys/contrib/zstd/lib/compress/
H A Dzstd_cwksp.h156 ZSTD_cwksp_alloc_phase_e phase; member
275 * Moves the cwksp to the next phase, and does any necessary allocations.
276 * cwksp initialization must necessarily go through each phase in order.
280 ZSTD_cwksp_internal_advance_phase(ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_internal_advance_phase() argument
282 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
283 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
285 if (ws->phase < ZSTD_cwksp_alloc_buffers && in ZSTD_cwksp_internal_advance_phase()
286 phase >= ZSTD_cwksp_alloc_buffers) { in ZSTD_cwksp_internal_advance_phase()
291 if (ws->phase < ZSTD_cwksp_alloc_aligned && in ZSTD_cwksp_internal_advance_phase()
292 phase >= ZSTD_cwksp_alloc_aligned) { in ZSTD_cwksp_internal_advance_phase()
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dsamsung,spi-peripheral-props.yaml23 The sampling phase shift to be applied on the miso line (to account
25 - 0: No phase shift.
26 - 1: 90 degree phase shift sampling.
27 - 2: 180 degree phase shift sampling.
28 - 3: 270 degree phase shift sampling.
/freebsd/sys/contrib/ck/include/
H A Dck_pflock.h32 * This is an implementation of phase-fair locks derived from the work
53 #define CK_PFLOCK_PHID 0x1 /* Phase ID bit. */
76 /* Migrate from write phase to read phase. */ in ck_pflock_write_unlock()
89 /* Acquire ownership of write-phase. */ in ck_pflock_write_lock()
97 * write-phase is pending. in ck_pflock_write_lock()
132 /* Wait for current write phase to complete. */ in ck_pflock_read_lock()
/freebsd/contrib/wpa/src/eap_peer/
H A Deap_ttls.c79 "EAP-TTLS: Do not require Phase 2 authentication"); in eap_ttls_parse_phase1()
83 "EAP-TTLS: Require Phase 2 authentication for initial connection"); in eap_ttls_parse_phase1()
87 "EAP-TTLS: Require Phase 2 authentication for all cases"); in eap_ttls_parse_phase1()
364 "Phase 2 EAP vendor %d method %d", in eap_ttls_phase2_select_eap_method()
431 "Phase 2 EAP vendor %d method %d (TNC)", in eap_ttls_phase2_request_eap_method()
464 "EAP-TTLS: failed to initialize Phase 2 EAP method %u:%u", in eap_ttls_phase2_request_eap_method()
485 "Phase 2 request (len=%lu)", (unsigned long) len); in eap_ttls_phase2_request_eap()
489 wpa_printf(MSG_DEBUG, "EAP-TTLS: Phase 2 EAP Request: type=%d", *pos); in eap_ttls_phase2_request_eap()
497 "EAP-TTLS: Too short Phase 2 request (expanded header) (len=%lu)", in eap_ttls_phase2_request_eap()
546 wpa_printf(MSG_DEBUG, "EAP-TTLS: Phase 2 MSCHAPV2 Request"); in eap_ttls_phase2_request_mschapv2()
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi-props.yaml90 phase in nanoseconds used for asynchronous read/write transactions.
94 phase in nanoseconds used for asynchronous multiplexed read/write
98 description: This property defines the duration of the data setup phase
106 description: This property defines the duration of the data hold phase
119 phase in nanoseconds used for asynchronous write transactions.
123 phase in nanoseconds used for asynchronous multiplexed write
128 phase in nanoseconds used for asynchronous write transactions.
135 description: This property defines the duration of the data hold phase
/freebsd/crypto/openssl/crypto/
H A Dself_test_core.c24 const char *phase; member
90 (char *)st->phase, 0); in self_test_setparams()
110 ret->phase = ""; in OSSL_SELF_TEST_new()
127 st->phase = OSSL_SELF_TEST_PHASE_START; in OSSL_SELF_TEST_onbegin()
142 st->phase = in OSSL_SELF_TEST_onend()
147 st->phase = OSSL_SELF_TEST_PHASE_NONE; in OSSL_SELF_TEST_onend()
164 st->phase = OSSL_SELF_TEST_PHASE_CORRUPT; in OSSL_SELF_TEST_oncorrupt_byte()
/freebsd/usr.bin/pom/
H A Dpom.633 .Nd display the phase of the moon
42 utility displays the current phase of the moon.
48 option to print just the phase as a percentage.
54 to specify a specific date and time for which the phase of the moon
60 has been specified, it will calculate the phase of the moon on that
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Ddlg,da9121.yaml13 Dialog Semiconductor DA9121 Single-channel 10A double-phase buck converter
14 Dialog Semiconductor DA9122 Double-channel 5A single-phase buck converter
15 Dialog Semiconductor DA9220 Double-channel 3A single-phase buck converter
16 Dialog Semiconductor DA9217 Single-channel 6A double-phase buck converter
17 Dialog Semiconductor DA9130 Single-channel 10A double-phase buck converter
18 Dialog Semiconductor DA9131 Double-channel 5A single-phase buck converter
19 Dialog Semiconductor DA9132 Double-channel 3A single-phase buck converter
20 Dialog Semiconductor DA9141 Single-channel 40A quad-phase buck converter
21 Dialog Semiconductor DA9142 Single-channel 20A double-phase buck converter
/freebsd/sys/contrib/openzfs/tests/zfs-tests/cmd/
H A Dxattrtest.c93 static int phase = PHASE_ALL; variable
103 " [-s <bytes>] [-p <path>] [-t <script> ] [-o <phase>]\n", in usage()
122 " --only -o <num> Only run phase N\n" in usage()
188 phase = strtol(optarg, NULL, 0); in parse_args()
189 if (phase <= PHASE_ALL || phase >= PHASE_INVAL) { in parse_args()
222 fprintf(stdout, "only: %d\n", phase); in parse_args()
292 post_hook(const char *phase) in post_hook() argument
294 char *argv[3] = { (char *)script, (char *)phase, NULL }; in post_hook()
689 if (phase == PHASE_ALL || phase == PHASE_CREATE) { in main()
695 if (phase == PHASE_ALL || phase == PHASE_SETXATTR) { in main()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIModeRegister.cpp82 // FirstInsertionPoint (if any) in this block. Calculated in Phase 1.
86 // this block, Calculated in Phase 1.
90 // block. Calculated in Phase 2.
94 // from all predecessor blocks. Calculated in Phase 2, and used by Phase 3.
97 // In Phase 1 we record the first instruction that has a mode requirement,
98 // which is used in Phase 3 if we need to insert a mode change.
238 // In Phase 1 we iterate through the instructions of the block and for each
250 // entry requirements in which case the insertion is deferred until Phase 3
263 // Phase 3. It is set to false once we have set FirstInsertionPoint, or when in processBlockPhase1()
315 // the insertion of the setreg to Phase 3 where we know whether or in processBlockPhase1()
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