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/linux/Documentation/devicetree/bindings/phy/
H A Dhisilicon,hix5hd2-sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,hix5hd2-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiancheng Xue <xuejiancheng@huawei.com>
14 const: hisilicon,hix5hd2-sata-phy
19 '#phy-cells':
22 hisilicon,peripheral-syscon:
23 description: Phandle of syscon used to control peripheral
26 hisilicon,power-reg:
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H A Dhisilicon,hi6220-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,hi6220-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Zhangfei Gao <zhangfei.gao@linaro.org>
14 const: hisilicon,hi6220-usb-phy
16 '#phy-cells':
19 phy-supply:
22 hisilicon,peripheral-syscon:
29 - |
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/linux/Documentation/devicetree/bindings/soc/cirrus/
H A Dcirrus,ep9301-syscon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/cirrus/cirrus,ep9301-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 Central resources are controlled by a set of software-locked registers,
15 which can be used to prevent accidental accesses. Syscon generates
16 the various bus and peripheral clocks and controls the system startup
19 The System Controller (Syscon) provides:
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/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-perictrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier peripheral block controller
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 Peripheral block implemented on Socionext UniPhier SoCs is an integrated
15 Peripheral block controller is a logic to control the component.
20 - enum:
21 - socionext,uniphier-ld4-perictrl
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/linux/Documentation/devicetree/bindings/mmc/
H A Dk3-dw-mshc.txt4 Read synopsys-dw-mshc.txt for more details
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
22 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
30 compatible = "hisilicon,hi4511-dw-mshc";
33 #address-cells = <1>;
34 #size-cells = <0>;
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/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dhi3798cv200-perictrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3798cv200-perictrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon Hi3798CV200 Peripheral Controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 The Hi3798CV200 Peripheral Controller controls peripherals, queries
19 - const: hisilicon,hi3798cv200-perictrl
20 - const: syscon
21 - const: simple-mfd
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/linux/Documentation/devicetree/bindings/bus/
H A Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
19 (mostly between peripheral devices and RAM, but also between DMA and
23 accessible by means of the Baikal-T1 System Controller.
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/linux/Documentation/devicetree/bindings/usb/
H A Dstarfive,jh7110-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb
18 starfive,stg-syscon:
19 $ref: /schemas/types.yaml#/definitions/phandle-array
21 - items:
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H A Dti,am62-usb.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI's AM62 wrapper module for the Synopsys USBSS-DRD controller
10 - Aswath Govindraju <a-govindraju@ti.com>
14 const: ti,am62-usb
19 - description: USB CFG register space
20 - description: USB PHY2 register space
24 power-domains:
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H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
27 - mediatek,mt8186-mtu3
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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8195-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
22 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
27 - enum:
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H A Dmediatek,pericfg.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Peripheral Configuration Controller
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
19 - items:
20 - enum:
21 - mediatek,mt2701-pericfg
22 - mediatek,mt2712-pericfg
23 - mediatek,mt6735-pericfg
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H A Dmediatek,mt8186-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
22 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
29 - enum:
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H A Dmediatek,mt8365-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markus Schneider-Pargmann <msp@baylibre.com>
15 The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
20 - enum:
21 - mediatek,mt8365-topckgen
22 - mediatek,mt8365-infracfg
23 - mediatek,mt8365-apmixedsys
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H A Dmediatek,mt8188-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Garmin Chang <garmin.chang@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
22 The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
29 - enum:
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/linux/drivers/phy/hisilicon/
H A Dphy-hi6220-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/mfd/syscon.h>
51 struct regmap *reg = priv->reg; in hi6220_phy_init()
63 struct regmap *reg = priv->reg; in hi6220_phy_setup()
94 dev_err(priv->dev, "failed to setup phy ret: %d\n", ret); in hi6220_phy_setup()
121 struct device *dev = &pdev->dev; in hi6220_phy_probe()
127 return -ENOMEM; in hi6220_phy_probe()
129 priv->dev = dev; in hi6220_phy_probe()
130 priv->reg = syscon_regmap_lookup_by_phandle(dev->of_node, in hi6220_phy_probe()
131 "hisilicon,peripheral-syscon"); in hi6220_phy_probe()
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/linux/Documentation/devicetree/bindings/reset/
H A Dnuvoton,ma35d1-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chi-Fang Li <cfli0@nuvoton.com>
11 - Jacky Huang <ychuang3@nuvoton.com>
14 The system reset controller can be used to reset various peripheral
20 - const: nuvoton,ma35d1-reset
21 - const: syscon
26 '#reset-cells':
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-clps711x.txt1 Serial Peripheral Interface on Cirrus Logic CL-PS71xx, EP72xx, EP73xx
4 - #address-cells: must be <1>
5 - #size-cells: must be <0>
6 - compatible: should include "cirrus,ep7209-spi"
7 - reg: Address and length of one register range
8 - interrupts: one interrupt line
9 - clocks: One entry, refers to the SPI bus clock
10 - cs-gpios: Specifies the gpio pins to be used for chipselects.
11 See: Documentation/devicetree/bindings/spi/spi-bus.txt
15 as compatible with "cirrus,ep7209-syscon3".
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,pil-info.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,pil-info.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm peripheral image loader relocation info
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 The Qualcomm peripheral image loader relocation memory region, in IMEM, is
19 const: qcom,pil-reloc-info
25 - compatible
26 - reg
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/linux/Documentation/devicetree/bindings/nvmem/
H A Dfsl,vf610-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/fsl,vf610-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: On-Chip OTP Memory for Freescale Vybrid
10 - Frank Li <Frank.Li@nxp.com>
13 - $ref: nvmem.yaml#
14 - $ref: nvmem-deprecated-cells.yaml
19 - enum:
20 - fsl,vf610-ocotp
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/linux/Documentation/devicetree/bindings/ata/
H A Dcortina,gemini-sata-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
19 const: cortina,gemini-sata-bridge
28 reset-names:
30 - const: sata0
31 - const: sata1
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/linux/Documentation/devicetree/bindings/sram/
H A Dqcom,imem.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 - enum:
20 - qcom,apq8064-imem
21 - qcom,msm8226-imem
22 - qcom,msm8974-imem
23 - qcom,msm8976-imem
24 - qcom,qcs404-imem
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Dsophgo,cv1800b-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/sophgo,cv1800b-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 contains a 32KHz oscillator and a Power-On-Reset (POR) sub-module, which can
14 power-on, power-off and reset.
19 through peripheral controllers.
22 https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM
25 - sophgo@lists.linux.dev
28 - $ref: /schemas/rtc/rtc.yaml#
[all …]
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
20 - const: fsl,imx8mp-hsio-blk-ctrl
21 - const: syscon
[all …]

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