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/freebsd/sys/contrib/device-tree/Bindings/dvfs/
H A Dperformance-domain.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic performance domains
10 - Sudeep Holla <sudeep.holla@arm.com>
13 This binding is intended for performance management of groups of devices or
14 CPUs that run in the same performance domain. Performance domains must not
15 be confused with power domains. A performance domain is defined by a set
16 of devices that always have to run at the same performance level. For a given
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
23 #size-cells = <2>;
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H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
63 enable-method = "spin-table";
64 cpu-release-addr = <0 0>; /* To be filled by loader */
65 next-level-cache = <&l2_cache_0>;
66 i-cache-size = <0x20000>;
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H A Dt8103.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
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H A Dt8112.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
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H A Dt600x-dieX.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 …compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
12 #performance-domain-cells = <0>;
16 …compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
18 #performance-domain-cells = <0>;
22 …compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
24 #performance-domain-cells = <0>;
27 DIE_NODE(pmgr): power-management@28e080000 {
28 compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
29 #address-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dapple,cluster-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
21 - items:
22 - enum:
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H A Dcpufreq-mediatek-hw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Yuan <hector.yuan@mediatek.com>
19 const: mediatek,cpufreq-hw
29 "#performance-domain-cells":
31 Number of cells in a performance domain specifier.
33 performance domains.
37 - compatible
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
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/freebsd/share/man/man4/
H A Dxen.45 .\" Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
46 "para-virtualized" as the x86 instruction set was not fully virtualizable.
47 Primarily, para-virtualization modifies the virtual memory system to use
49 modify the TLB, although para-virtualized device drivers were also required
54 supported; this is referred to as hardware-assisted virtualization (HVM and PVH).
56 peripherals, or para-virtualized drivers, which are aware of virtualization,
57 and hence able to optimize certain behaviors to improve performance or
59 PVH configurations rely on para-virtualized drivers exclusively for IO.
62 Para-virtualized device drivers are required in order to support certain
66 These para-virtualized drivers are supported:
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,sm8350-videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,videocc-sm8350.h
18 include/dt-bindings/reset/qcom,videocc-sm8350.h
23 - qcom,sc8280xp-videocc
24 - qcom,sm8350-videocc
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H A Dqcom,sm8450-videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
11 - Jagadeesh Kona <quic_jkona@quicinc.com>
15 domains on SM8450.
18 include/dt-bindings/clock/qcom,sm8450-videocc.h
19 include/dt-bindings/clock/qcom,sm8650-videocc.h
24 - qcom,sm8450-videocc
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H A Dqcom,sm8150-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8150-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
14 power domains on SM8150.
16 See also:: include/dt-bindings/clock/qcom,sm8150-camcc.h
20 const: qcom,sm8150-camcc
27 - description: Board XO source
28 - description: Camera AHB clock from GCC
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H A Dqcom,sm6375-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
14 domains on Qualcomm SoCs.
16 See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
21 - qcom,sm6375-gpucc
25 - description: Board XO source
26 - description: GPLL0 main branch source
[all …]
H A Dqcom,qcm2290-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,qcm2290-gpucc.h
21 const: qcom,qcm2290-gpucc
28 - description: AHB interface clock,
29 - description: SoC CXO clock
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H A Dqcom,sm8450-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
11 - Jagadeesh Kona <quic_jkona@quicinc.com>
15 domains on SM8450.
18 include/dt-bindings/clock/qcom,sc8280xp-camcc.h
19 include/dt-bindings/clock/qcom,sm8450-camcc.h
20 include/dt-bindings/clock/qcom,sm8550-camcc.h
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H A Dqcom,sm8450-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 domains on SM8450.
16 See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
21 - qcom,sm8450-dispcc
26 - description: Board XO source
27 - description: Board Always On XO source
[all …]
H A Dqcom,videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,videocc-sc7180.h
18 include/dt-bindings/clock/qcom,videocc-sc7280.h
19 include/dt-bindings/clock/qcom,videocc-sdm845.h
20 include/dt-bindings/clock/qcom,videocc-sm8150.h
21 include/dt-bindings/clock/qcom,videocc-sm8250.h
[all …]
H A Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
14 domains on SM8150/SM8250/SM8350.
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
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/freebsd/sys/contrib/device-tree/include/dt-bindings/power/
H A Dqcom-rpmpd.h1 /* SPDX-License-Identifier: GPL-2.0 */
218 /* SDM845 Power Domain performance levels */
244 /* MDM9607 Power Domains */
257 /* MSM8939 Power Domains */
356 /* QCS404 Power Domains */
365 /* SDM660 Power Domains */
377 /* SM6115 Power Domains */
387 /* SM6125 Power Domains */
395 /* QCM2290 Power Domains */
405 /* RPM SMD Power Domain performance levels */
/freebsd/sys/contrib/device-tree/Bindings/power/
H A Dapple,pmgr-pwrstate.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
13 - $ref: power-domain.yaml#
18 performance features. This binding describes the device power
23 Documentation/devicetree/bindings/power/power-domain.yaml.
25 represented via power-domains relationships between these nodes.
28 for the top-level PMGR node documentation.
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
24 - nxp,imx8mp-dw100
34 - description: The AXI clock
35 - description: The AHB clock
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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/freebsd/sys/contrib/device-tree/Bindings/arm/apple/
H A Dapple,pmgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
15 performance features. This node represents the PMGR as a syscon,
16 with sub-nodes representing individual features.
20 pattern: "^power-management@[0-9a-f]+$"
24 - enum:
25 - apple,t8103-pmgr
26 - apple,t8112-pmgr
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