Lines Matching +full:performance +full:- +full:domains
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/apple-aic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/apple.h>
17 interrupt-parent = <&aic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 clkref: clock-ref {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <24000000>;
25 clock-output-names = "clkref";
29 #address-cells = <2>;
30 #size-cells = <0>;
35 cpu-release-addr = <0 0>; /* To be filled in by loader */
36 performance-domains = <&cpufreq>;
37 operating-points-v2 = <&typhoon_opp>;
38 enable-method = "spin-table";
40 next-level-cache = <&l2_cache>;
41 i-cache-size = <0x10000>;
42 d-cache-size = <0x10000>;
48 cpu-release-addr = <0 0>; /* To be filled in by loader */
49 performance-domains = <&cpufreq>;
50 operating-points-v2 = <&typhoon_opp>;
51 enable-method = "spin-table";
53 next-level-cache = <&l2_cache>;
54 i-cache-size = <0x10000>;
55 d-cache-size = <0x10000>;
58 l2_cache: l2-cache {
60 cache-level = <2>;
61 cache-unified;
62 cache-size = <0x100000>;
66 typhoon_opp: opp-table {
67 compatible = "operating-points-v2";
70 opp-hz = /bits/ 64 <300000000>;
71 opp-level = <1>;
72 clock-latency-ns = <300>;
75 opp-hz = /bits/ 64 <396000000>;
76 opp-level = <2>;
77 clock-latency-ns = <50000>;
80 opp-hz = /bits/ 64 <600000000>;
81 opp-level = <3>;
82 clock-latency-ns = <29000>;
85 opp-hz = /bits/ 64 <840000000>;
86 opp-level = <4>;
87 clock-latency-ns = <29000>;
90 opp-hz = /bits/ 64 <1128000000>;
91 opp-level = <5>;
92 clock-latency-ns = <36000>;
95 opp-hz = /bits/ 64 <1392000000>;
96 opp-level = <6>;
97 clock-latency-ns = <42000>;
101 opp-hz = /bits/ 64 <1512000000>;
102 opp-level = <7>;
103 clock-latency-ns = <49000>;
109 compatible = "simple-bus";
110 #address-cells = <2>;
111 #size-cells = <2>;
112 nonposted-mmio;
115 cpufreq: performance-controller@202220000 {
116 compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq";
118 #performance-domain-cells = <0>;
122 compatible = "apple,s5l-uart";
124 reg-io-width = <4>;
125 interrupt-parent = <&aic>;
127 /* Use the bootloader-enabled clocks for now. */
129 clock-names = "uart", "clk_uart_baud0";
130 power-domains = <&ps_uart0>;
135 compatible = "apple,s5l-uart";
137 reg-io-width = <4>;
138 interrupt-parent = <&aic>;
140 /* Use the bootloader-enabled clocks for now. */
142 clock-names = "uart", "clk_uart_baud0";
143 power-domains = <&ps_uart6>;
147 pmgr: power-management@20e000000 {
148 compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
149 #address-cells = <1>;
150 #size-cells = <1>;
156 compatible = "apple,t7000-wdt", "apple,wdt";
159 interrupt-parent = <&aic>;
163 aic: interrupt-controller@20e100000 {
164 compatible = "apple,t7000-aic", "apple,aic";
166 #interrupt-cells = <3>;
167 interrupt-controller;
168 power-domains = <&ps_aic>;
172 compatible = "apple,t7000-dwi-bl", "apple,dwi-bl";
174 power-domains = <&ps_dwi>;
179 compatible = "apple,t7000-pinctrl", "apple,pinctrl";
181 power-domains = <&ps_gpio>;
183 gpio-controller;
184 #gpio-cells = <2>;
185 gpio-ranges = <&pinctrl 0 0 208>;
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 interrupt-parent = <&aic>;
202 compatible = "arm,armv8-timer";
203 interrupt-parent = <&aic>;
204 interrupt-names = "phys", "virt";
211 #include "t7000-pmgr.dtsi"