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/linux/drivers/media/pci/intel/ipu6/
H A D	ipu6.h	`1 /* SPDX-License-Identifier: GPL-2.0-only / 2 / Copyright (C) 2013 - 2024 Intel Corporation / 11 #include "ipu6-buttress.h" 17 #define IPU6_NAME "intel-ipu6" 35 IPU6 - TGL 36 * IPU6SE - JSL 37 * IPU6EP - ADL/RPL 38 * IPU6EP_MTL - MTL 96 /* The firmware is accessible within the first 2 GiB only in non-secure mode. / 116 Threshold values are pre-defined and are arrived at after performance [all …]`
/linux/drivers/staging/vc04_services/vchiq-mmal/
H A D	mmal-msg-format.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 19 #include "mmal-msg-common.h" 27 u32 bits_per_sample; / Bits per sample / 39 FourCC specifying the color space of the video stream. See the 40 * MmalColorSpace "pre-defined color spaces" for some examples. 56 /* Definition of an elementary stream format (MMAL_ES_FORMAT_T) / 61 stream. 65 * stream. 70 * elementary stream 73 u32 bitrate; /* Bitrate in bits per second */ [all …]`
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffe [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffe [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffe [all...]
/linux/drivers/staging/media/atomisp/pci/
H A D	ia_css_stream_public.h	1 /* SPDX-License-Identifier: GPL-2.0 / 29 IA_CSS_INPUT_MODE_FIFO, /* data from input-fifo / 30 IA_CSS_INPUT_MODE_TPG, /* data from test-pattern generator / 31 IA_CSS_INPUT_MODE_PRBS, /* data from pseudo-random bit stream / 44 stream / 59 enum atomisp_input_format format; / Format of input stream. This data 62 int linked_isys_stream_id; / default value is -1, other value means 74 enum atomisp_input_format format; /** Format of input stream. This data 80 /* Input stream description. This describes how input will flow into the 106 unsigned int pixels_per_clock; /** Number of pixels per clock, which can be [all …]
/linux/Documentation/userspace-api/media/v4l/
H A D	pixfmt-compressed.rst	1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later 8 .. _compressed-formats: 18 .. flat-table:: Compressed Image Formats 19 :header-rows: 1 20 :stub-columns: 0 23 * - Identifier 24 - Code 25 - Details 26 * .. _V4L2-PIX-FMT-JPEG: 28 - ``V4L2_PIX_FMT_JPEG`` [all …]
/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes… 28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 36 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 105 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… 114 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 160 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca… [all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	frontend.json	11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 23 …Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes… 28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 36 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 105 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… 114 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.… 160 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca… [all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A D	frontend.json	7 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 36 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 53 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 93 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… 102 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 153 … event counts cycles during which the microcode sequencer assisted the Front-end in delivering uop… 158 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … [all …]
/linux/tools/perf/pmu-events/arch/x86/haswell/
H A D	frontend.json	7 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 36 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", 53 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 93 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… 102 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 153 … event counts cycles during which the microcode sequencer assisted the Front-end in delivering uop… 158 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … [all …]
/linux/sound/usb/line6/
H A D	pcm.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 5 Copyright (C) 2004-2010 Markus Grabner (line6@grabner-graz.at) 20 number of USB frames per URB 21 The Line 6 Windows driver always transmits two frames per packet, but 23 with only one frame per packet. 37 #define get_substream(line6pcm, stream) \ argument 38 (line6pcm->pcm->streams[stream].substream) 49 capture and playback stream, which must be shared between these 54 or capture stream. Both can contain the bit flag corresponding to 60 the running flag indicates whether the stream is running. [all …]
/linux/sound/firewire/dice/
H A D	dice-interface.h	1 /* SPDX-License-Identifier: GPL-2.0 / 11 block read transactions with at least quadlet-aligned offset and length. 12 * Writes are not allowed except where noted; quadlet-sized registers must be 15 * All values are in big endian. The DICE firmware runs on a little-endian CPU 16 * and just byte-swaps _all_ quadlets on the bus, so values without endianness 17 * (e.g. strings) get scrambled and must be byte-swapped again by the driver. 32 * size values are measured in quadlets. Read-only. 50 * Stores the full 64-bit address (node ID and offset in the node's address 60 * A bitmask with asynchronous events; read-only. When any event(s) happen, 74 /* Other bits may be used for device-specific events. */ [all …]
/linux/include/linux/soundwire/
H A D	sdw.h	1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) / 2 / Copyright(c) 2015-17 Intel Corporation. / 83 / sample packaging for block. It can be per port or per channel / 88 enum sdw_slave_status - Slave status 106 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepar 1109 sdw_stream_add_slave(struct sdw_slave * slave,struct sdw_stream_config * stream_config,const struct sdw_port_config * port_config,unsigned int num_ports,struct sdw_stream_runtime * stream) sdw_stream_add_slave() argument 1116 sdw_stream_remove_slave(struct sdw_slave * slave,struct sdw_stream_runtime * stream) sdw_stream_remove_slave() argument [all...]
/linux/include/linux/
H A D	slimbus.h	1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2011-2017, The Linux Foundation 16 * struct slim_eaddr - Enumeration address for a SLIMbus device 30 * enum slim_device_status - slim device status 44 * struct slim_device - Slim device handle. 49 * @laddr: 1-byte Logical address of this device. 52 * @stream_list_lock: lock to protect the stream list 56 * Pointer to this structure is used by client-driver as a handle. 72 * struct slim_driver - SLIMbus 'generic device' (slave) device driver 78 * - The device reports present and gets a laddr assigned [all …]
/linux/Documentation/devicetree/bindings/media/
H A D	cdns,csi2tx.txt	1 Cadence MIPI-CSI2 TX controller 4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to 8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3" 9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1 10 - reg: base address and size of the memory mapped region 11 - clocks: phandles to the clocks driving the controller 12 - clock-names: must contain: 15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream 19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set 20 - phy-names: must contain "dphy" [all …]
/linux/tools/perf/pmu-events/arch/x86/skylake/
H A D	frontend.json	7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th… 46 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-… 58 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st… 97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 104 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no… [all …]
/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th… 46 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-… 58 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st… 97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 104 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no… [all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A D	frontend.json	7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch… 16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 34 …Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed th… 46 …unts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-… 58 …d a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means st… 97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 104 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no… [all …]
/linux/kernel/bpf/
H A D	stream.c	1 // SPDX-License-Identifier: GPL-2.0-only 15 * Simple per-CPU NMI-safe bump allocation mechanism, backed by the NMI-safe 17 * stash it in a local per-CP 200 bpf_stream_consume_capacity(struct bpf_stream * stream,int len) bpf_stream_consume_capacity() argument 211 bpf_stream_release_capacity(struct bpf_stream * stream,struct bpf_stream_elem * elem) bpf_stream_release_capacity() argument 218 bpf_stream_push_str(struct bpf_stream * stream,const char * str,int len) bpf_stream_push_str() argument 248 bpf_stream_backlog_peek(struct bpf_stream * stream) bpf_stream_backlog_peek() argument 253 bpf_stream_backlog_pop(struct bpf_stream * stream) bpf_stream_backlog_pop() argument 265 bpf_stream_backlog_fill(struct bpf_stream * stream) bpf_stream_backlog_fill() argument 298 bpf_stream_read(struct bpf_stream * stream,void __user * buf,int len) bpf_stream_read() argument 344 struct bpf_stream stream; bpf_prog_stream_read() local 366 struct bpf_stream stream; bpf_stream_vprintk() local 457 struct bpf_stream *stream; bpf_stream_stage_commit() local [all...]
/linux/sound/virtio/
H A D	virtio_chmap.c	1 // SPDX-License-Identifier: GPL-2.0+ 3 * virtio-snd: Virtio sound device 10 /* VirtIO->ALSA channel position map / 52 virtsnd_chmap_parse_cfg() - Parse the channel map configuration. 58 * Return: 0 on success, -errno on failure. 62 struct virtio_device vdev = snd->vdev; in virtsnd_chmap_parse_cfg() 66 virtio_cread_le(vdev, struct virtio_snd_config, chmaps, &snd->nchmaps); in virtsnd_chmap_parse_cfg() 67 if (!snd->nchmaps) in virtsnd_chmap_parse_cfg() 70 snd->chmaps = devm_kcalloc(&vdev->dev, snd->nchmaps, in virtsnd_chmap_parse_cfg() 71 sizeof(snd->chmaps), GFP_KERNEL); in virtsnd_chmap_parse_cfg() [all …]
/linux/drivers/media/platform/samsung/s5p-mfc/
H A D	regs-mfc.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 15 #define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) 16 #define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4) 84 / VC-1 decoding / 157 / Channel & stream interface register / 177 #define S5P_FIMV_SI_CH0_SB_ST_ADR 0x2044 / start addr of stream buf / 178 #define S5P_FIMV_SI_CH0_SB_FRM_SIZE 0x2048 / size of stream buf / 183 #define S5P_FIMV_SI_CH1_SB_ST_ADR 0x2084 / start addr of stream buf / 184 #define S5P_FIMV_SI_CH1_SB_FRM_SIZE 0x2088 / size of stream buf / 189 #define S5P_FIMV_CRC_LUMA0 0x2030 / luma crc data per frame [all …]
/linux/drivers/acpi/
H A D	nhlt.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright(c) 2023-2024 Intel Corporation 28 * acpi_nhlt_get_gbl_table - Retrieve a pointer to the first NHLT table. 47 * acpi_nhlt_put_gbl_table - Release the global NHLT table. 56 * acpi_nhlt_endpoint_match - Verify if an endpoint matches criteria. 60 * @dir: stream direction. 72 (link_type < 0 \|\| ep->link_type == link_type) && in acpi_nhlt_endpoint_match() 73 (dev_type < 0 \|\| ep->device_type == dev_type) && in acpi_nhlt_endpoint_match() 74 (bus_id < 0 \|\| ep->virtual_bus_id == bus_id) && in acpi_nhlt_endpoint_match() 75 (dir < 0 \|\| ep->direction == dir); in acpi_nhlt_endpoint_match() [all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	frontend.json	7 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 30 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 48 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 52 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 106 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 111 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… [all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	frontend.json	7 "PublicDescription": "Number of front end re-steers due to BPU misprediction.", 12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 30 …"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stre… 48 …"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB… 52 …"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTL… 66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 106 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 111 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.… [all …]

12 3 4 5 6 7 8 9 10 >>...27