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/linux/include/drm/display/
H A Ddrm_dsc.h1 /* SPDX-License-Identifier: MIT
45 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
67 * struct drm_dsc_config - Parameters required to configure DSC
75 * Bits per component for previous reconstructed line buffer
79 * @bits_per_component: Bits per component to code (8/10/12)
84 * Flag to indicate if RGB - YCoCg conversion is needed
89 * @slice_count: Number fo slices per line used by the DSC encoder
93 * @slice_width: Width of each slice in pixels
97 * @slice_height: Slice height in pixels
124 * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4
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/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-compressed.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 .. _compressed-formats:
18 .. flat-table:: Compressed Image Formats
19 :header-rows: 1
20 :stub-columns: 0
23 * - Identifier
24 - Code
25 - Details
26 * .. _V4L2-PIX-FMT-JPEG:
28 - ``V4L2_PIX_FMT_JPEG``
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H A Dext-ctrls-codec.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _codec-controls:
24 .. _mpeg-control-id:
27 -----------------
35 .. _v4l2-mpeg-stream-type:
40 enum v4l2_mpeg_stream_type -
41 The MPEG-1, -2 or -4 output stream type. One cannot assume anything
48 .. flat-table::
49 :header-rows: 0
50 :stub-columns: 0
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H A Dext-ctrls-codec-stateless.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _codec-stateless-controls:
18 .. _codec-stateless-control-id:
23 .. _v4l2-codec-stateless-h264:
27 bitstream) for the associated H264 slice data. This includes the
43 .. flat-table:: struct v4l2_ctrl_h264_sps
44 :header-rows: 0
45 :stub-columns: 0
48 * - __u8
49 - ``profile_idc``
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/linux/drivers/gpu/drm/xe/
H A Dxe_gt_ccs_mode.c1 // SPDX-License-Identifier: MIT
36 * slice 0, 1, 2, 3: ccs0 in __xe_gt_apply_ccs_mode()
39 * slice 0, 2: ccs0 in __xe_gt_apply_ccs_mode()
40 * slice 1, 3: ccs1 in __xe_gt_apply_ccs_mode()
43 * slice 0: ccs0 in __xe_gt_apply_ccs_mode()
44 * slice 1: ccs1 in __xe_gt_apply_ccs_mode()
45 * slice 2: ccs2 in __xe_gt_apply_ccs_mode()
46 * slice 3: ccs3 in __xe_gt_apply_ccs_mode()
48 for (width = num_slices / num_engines; width; width--) { in __xe_gt_apply_ccs_mode()
53 if (hwe->class != XE_ENGINE_CLASS_COMPUTE) in __xe_gt_apply_ccs_mode()
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/linux/Documentation/accel/qaic/
H A Dqaic.rst1 .. SPDX-License-Identifier: GPL-2.0-only
14 --------------------
21 non-empty and generate MSIs at a rate equivalent to the speed of the
24 MSIs per second. It has been observed that most systems cannot tolerate this
37 generates 100k IRQs per second (per /proc/interrupts) is reduced to roughly 64
42 ---------------
72 QAIC handles and enforces the required little endianness and 64-bit alignment,
96 QAIC creates an accel device per physical PCIe device. This accel device exists
121 This IOCTL allows userspace to slice a BO in preparation for sending the BO
128 call is non-blocking. Success only indicates that the BOs have been queued
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/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_classifier.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
20 /* Filter 1 - FT1 */
31 (offs[slice].ft1_slot_base + FT1_SLOT_SIZE * (n) + (reg))
51 /* Filter 3 - FT3 */
66 (offs[slice].ft3_slot_base + FT3_SLOT_SIZE * (n) + (reg))
74 #define RX_CLASS_N_REG(slice, n, reg) \ argument
75 (offs[slice].rx_class_base + RX_CLASS_EN_SIZE * (n) + (reg))
80 #define RX_CLASS_GATES_N_REG(slice, n) \ argument
81 (offs[slice].rx_class_gates_base + RX_CLASS_GATES_SIZE * (n))
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H A Dicssg_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
33 #define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */
45 #define PRUETH_SWITCH_FDB_MASK ((SIZE_OF_FDB / NUMBER_OF_FDB_BUCKET_ENTRIES) - 1)
124 /* SR1.0-specific bits */
147 __le32 tx_rate_lim_en; /* Bitmask: Egress rate limit en per thread */
160 * - ss: sequence number. Currently not used by driver.
167 * - ss: sequence number. Currently not used by driver.
168 * - P: port number (for switch mode).
169 * - N: Speed/Duplex state:
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H A Dicssg_config.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
79 * struct map - ICSSG Queue Map
112 struct prueth *prueth = emac->prueth; in icssg_config_mii_init_fw_offload()
117 mii_rt = prueth->mii_rt; in icssg_config_mii_init_fw_offload()
128 if (emac->phy_if == PHY_INTERFACE_MODE_MII && mii == ICSS_MII1) in icssg_config_mii_init_fw_offload()
130 else if (emac->phy_if != PHY_INTERFACE_MODE_MII && mii == ICSS_MII0) in icssg_config_mii_init_fw_offload()
139 struct prueth *prueth = emac->prueth; in icssg_config_mii_init()
140 int slice = prueth_emac_slice(emac); in icssg_config_mii_init() local
144 mii_rt = prueth->mii_rt; in icssg_config_mii_init()
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H A Dicssg_prueth_sr1.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
26 #include "../k3-cppi-desc-pool.h"
34 * situation. So use Q0-Q2 as data queues and Q3 as management queue
39 * Allocate 4 MTU buffers per data queue. Firmware requires
55 int slice) in icssg_config_sr1() argument
62 config.addr_lo = cpu_to_le32(lower_32_bits(prueth->msmcram.pa)); in icssg_config_sr1()
63 config.addr_hi = cpu_to_le32(upper_32_bits(prueth->msmcram.pa)); in icssg_config_sr1()
64 config.rx_flow_id = cpu_to_le32(emac->rx_flow_id_base); /* flow id for host port */ in icssg_config_sr1()
65 config.rx_mgr_flow_id = cpu_to_le32(emac->rx_mgm_flow_id_base); /* for mgm ch */ in icssg_config_sr1()
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/linux/block/partitions/
H A Dmsdos.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 1991-1998 Linus Torvalds
9 * in the early extended-partition checks and added DM partitions
16 * More flexible handling of extended partitions - aeb, 950831
20 * Re-organised Feb 1998 Russell King
43 return (sector_t)get_unaligned_le32(&p->nr_sects); in nr_sects()
48 return (sector_t)get_unaligned_le32(&p->start_sect); in start_sect()
53 return (p->sys_ind == DOS_EXTENDED_PARTITION || in is_extended_partition()
54 p->sys_ind == WIN98_EXTENDED_PARTITION || in is_extended_partition()
55 p->sys_ind == LINUX_EXTENDED_PARTITION); in is_extended_partition()
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/linux/Documentation/ABI/testing/
H A Ddebugfs-driver-qat_telemetry4 Contact: qat-linux@intel.com
16 * 1-4: telemetry is enabled and running
40 Contact: qat-linux@intel.com
64 util_cpr<N> utilization of Compression slice N [%]
65 exec_cpr<N> execution count of Compression slice N
66 util_xlt<N> utilization of Translator slice N [%]
67 exec_xlt<N> execution count of Translator slice N
68 util_dcpr<N> utilization of Decompression slice N [%]
69 exec_dcpr<N> execution count of Decompression slice N
72 util_ucs<N> utilization of UCS slice N [%]
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/linux/drivers/media/platform/st/sti/hva/
H A Dhva-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "hva-hw.h"
32 /* source buffer copy in YUV 420 MB-tiled format with size=16*256*3/2 */
154 * @frame_num: the parameter to be written in the slice header
160 * @slice_size_type: 0 = no constraint to close the slice
161 * 1= a slice is closed as soon as the slice_mb_size limit
163 * 2= a slice is closed as soon as the slice_byte_size limit
165 * 3= a slice is closed as soon as either the slice_byte_size
167 * @slice_mb_size: defines the slice size in number of macroblocks
169 * @ir_param_option: defines the number of macroblocks per frame to be
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/linux/drivers/media/platform/samsung/s5p-mfc/
H A Dregs-mfc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)
16 #define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)
84 /* VC-1 decoding */
189 #define S5P_FIMV_CRC_LUMA0 0x2030 /* luma crc data per frame
191 #define S5P_FIMV_CRC_CHROMA0 0x2034 /* chroma crc data per frame
193 #define S5P_FIMV_CRC_LUMA1 0x2038 /* luma crc data per bottom
195 #define S5P_FIMV_CRC_CHROMA1 0x203c /* chroma crc data per bottom
265 #define S5P_FIMV_ENC_SI_SLICE_TYPE 0x2010 /* slice type(I/P/B/IDR) */
291 #define S5P_FIMV_ENC_MSLICE_CTRL 0xc50c /* multi slice control */
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-consumer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
25 $ref: /schemas/types.yaml#/definitions/phandle-array
32 firmware-name:
33 $ref: /schemas/types.yaml#/definitions/string-array
41 ti,pruss-gp-mux-sel:
42 $ref: /schemas/types.yaml#/definitions/uint32-array
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/linux/sound/pci/au88x0/
H A Dau88x0_a3d.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 vortex_t *vortex = (vortex_t *) (a->vortex); in a3dsrc_SetTimeConsts()
25 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
26 a3d_addrA(a->slice, a->source, A3D_A_HrtfTrackTC), HrtfTrack); in a3dsrc_SetTimeConsts()
27 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
28 a3d_addrA(a->slice, a->source, A3D_A_ITDTrackTC), ItdTrack); in a3dsrc_SetTimeConsts()
29 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
30 a3d_addrA(a->slice, a->source, A3D_A_GainTrackTC), GTrack); in a3dsrc_SetTimeConsts()
31 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
32 a3d_addrA(a->slice, a->source, A3D_A_CoeffTrackTC), CTrack); in a3dsrc_SetTimeConsts()
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu_debugfs.c1 // SPDX-License-Identifier: MIT
19 struct intel_uncore *uncore = gt->uncore; in cherryview_sseu_device_status()
36 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
37 sseu->subslice_mask.hsw[0] |= BIT(ss); in cherryview_sseu_device_status()
42 sseu->eu_total += eu_cnt; in cherryview_sseu_device_status()
43 sseu->eu_per_subslice = max_t(unsigned int, in cherryview_sseu_device_status()
44 sseu->eu_per_subslice, eu_cnt); in cherryview_sseu_device_status()
53 struct intel_uncore *uncore = gt->uncore; in gen11_sseu_device_status()
54 const struct intel_gt_info *info = &gt->info; in gen11_sseu_device_status()
58 for (s = 0; s < info->sseu.max_slices; s++) { in gen11_sseu_device_status()
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H A Dintel_gt_types.h1 /* SPDX-License-Identifier: MIT */
51 * direct reads to a slice/subslice that are valid for the 'subslice' class
54 * need to explicitly re-steer reads of registers of the other type.
56 * Only the replication types that may need additional non-default steering
69 * will always return a non-terminated value at instance (0, 0). We'll
250 * Should be taken before uncore->lock in cases where both are desired.
255 * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
271 /* Media engine access to SFC per instance */
274 /* Slice/subslice/EU info */
291 /* sysfs defaults per gt */
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/linux/rust/kernel/
H A Duaccess.rs1 // SPDX-License-Identifier: GPL-2.0
20 /// A pointer to an area in userspace memory, which can be either read-only or read-write.
23 /// the bound of the slice or unmapped addresses) will return [`EFAULT`]. Concurrent access,
28 /// well-defined. Kernelspace code should validate its copy of data after completing a read, and not
31 /// These APIs are designed to make it difficult to accidentally write TOCTOU (time-of-check to
32 /// time-of-use) bugs. Every time a memory location is read, the reader's position is advanced by
39 /// If double-fetching a memory location is necessary for some reason, then that is done by creating
51 /// fn bytes_add_one(uptr: UserPtr, len: usize) -> Result {
66 /// Example illustrating a TOCTOU (time-of-check to time-of-use) bug.
73 /// fn is_valid(uptr: UserPtr, len: usize) -> Result<bool> {
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/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json25 "BriefDescription": "Cycles in which the SRQ has at least one (out of four) empty slice"
65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
125 "BriefDescription": "TEND latency per thread"
200 "BriefDescription": "Read-write data cache collisions"
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
395 …-word boundary, which causes it to require an additional slice than than what normally would be re…
430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
450 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
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/linux/tools/sched_ext/
H A Dscx_flatcg.bpf.c1 /* SPDX-License-Identifier: GPL-2.0 */
4 * hierarchical weight-based cgroup CPU control by flattening the cgroup
24 * So, instead of hierarchically scheduling level-by-level, we can consider it
44 * cgroup-internal scheduling can be switched to FIFO with the -f option.
137 return (dividend + divisor - 1) / divisor; in div_round_up()
147 return cgc_a->cvtime < cgc_b->cvtime; in cgv_node_less()
169 scx_bpf_error("cgrp_ctx lookup failed for cgid %llu", cgrp->kn->id); in find_cgrp_ctx()
196 if (!cgc->nr_active) { in cgrp_refresh_hweight()
201 if (cgc->hweight_gen == hweight_gen) { in cgrp_refresh_hweight()
207 bpf_for(level, 0, cgrp->level + 1) { in cgrp_refresh_hweight()
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/linux/Documentation/admin-guide/perf/
H A Dqcom_l3_pmu.rst7 by all cores within a socket. Each slice is exposed as a separate uncore perf
14 consisting of one CPU per socket which will be used to handle all the PMU
23 perf stat -e l3cache_0_0/read-miss,lc/
26 "perf record" will not work. Per-task perf sessions are not supported.
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c86 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
89 (clk_mgr->regs->reg)
141 /* fine-grained, only min and max */ in dcn32_init_single_clock()
151 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn32_init_single_clock()
169 if (!clk_mgr_base->bw_params) in dcn32_init_clocks()
172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks()
174 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn32_init_clocks()
175 clk_mgr_base->clks.p_state_change_support = true; in dcn32_init_clocks()
176 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn32_init_clocks()
177 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; in dcn32_init_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddsc.h41 enum dc_color_depth color_depth; /* Bits per component */
47 /* Output parameters for configuring DSC-related part of OPTC */
49 uint32_t slice_width; /* Slice width in pixels */
50 uint32_t bytes_per_pixel; /* Bytes per pixel in u3.28 format */
76 uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
/linux/drivers/gpu/drm/i915/display/
H A Dintel_bw.c1 // SPDX-License-Identifier: MIT
46 struct drm_i915_private *i915 = to_i915(display->drm); in dg1_mchbar_read_qgv_point_info()
50 val = intel_uncore_read(&i915->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC); in dg1_mchbar_read_qgv_point_info()
56 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); in dg1_mchbar_read_qgv_point_info()
58 val = intel_uncore_read(&i915->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); in dg1_mchbar_read_qgv_point_info()
60 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
62 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
63 return -EINVAL; in dg1_mchbar_read_qgv_point_info()
65 val = intel_uncore_read(&i915->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); in dg1_mchbar_read_qgv_point_info()
66 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
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