| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-port
[all...] |
| H A D | renesas,rza1-pinctrl.txt | 1 Renesas RZ/A1 combined Pin and GPIO controller
3 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
5 Pin multiplexing and GPIO configuration is performed on a per-pin basis
6 writing configuration values to per-port register sets.
9 Up to 8 different alternate function modes exist for each single pin.
11 Pin controller node
12 -------------------
15 - compatible: should be:
16 - "renesas,r7s72100-ports": for RZ/A1H
17 - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
[all …]
|
| H A D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
[all …]
|
| H A D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
|
| H A D | pinctrl-st.txt | 1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
6 the pin to different hardware blocks.
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
[all …]
|
| H A D | pinctrl-single.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Controller with a Single Register for One or More Pins
10 - Tony Lindgren <tony@atomide.com>
13 Some pin controller devices use a single register for one or more pins. The
14 range of pin control registers can vary from one to many for each controller
16 kind of pin controller instances.
21 - enum:
[all …]
|
| H A D | pinctrl-rk805.txt | 5 Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
7 including the meaning of the phrase "pin configuration node".
10 --------
[all...] |
| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
6 controlled are organized in groups, so no actual pin information is
9 A pin-controller node should contain subnodes representing the pin group
10 configurations, one per function. Each subnode has the group name and
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
[all …]
|
| H A D | renesas,rza2-pinctrl.txt | 1 Renesas RZ/A2 combined Pin and GPIO controller
3 The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
4 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
7 Up to 8 different alternate function modes exist for each single pin.
9 Pin controller node
10 -------------------
13 - compatible: shall be:
14 - "renesas,r7s9210-pinctrl": for RZ/A2M
15 - reg
16 Address base and length of the memory area where the pin controller
[all …]
|
| H A D | renesas,rza2-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctr
[all...] |
| H A D | allwinner,sun4i-a10-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Pin Controlle
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | tda1997x.txt | 1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | adi,adv7511.txt | 2 ------------------------------------------------
11 - compatible: Should be one of:
18 - reg: I2C slave addresses
32 - adi,input-depth: Number of bits per color component at the input (8, 10 or
34 - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or
36 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per
37 pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel,
43 - adi,input-style: The input components arrangement variant (1, 2 or 3), as
45 - adi,input-justification: The input bit justification ("left", "evenly",
48 - avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
[all …]
|
| H A D | adi,adv7511.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
37 reg-names:
40 needing a non-default address.
43 - const: main
[all …]
|
| /freebsd/share/man/man4/man4.arm/ |
| H A D | am335x_dmtpps.4 | 31 .Nd RFC 2783 Pulse Per Second API driver for AM335x systems
37 .Cd hw.am335x_dmtpps.input="pin name"
43 capture of Pulse Per Second (PPS) signals emitted by GPS receivers
75 The driver uses system pin configuration to determine which hardware
77 Configure the timer input pin in the system's FDT data, or by
78 supplying the pin name using a tunable variable in
87 tunable variable to the name of the input pin, one of the following:
89 .Bl -tag -width "GPMC_ADVn_ALE MMMM" -offset MMMM -compact
92 .It P8-7
93 DMTimer4; Beaglebone P8 header pin 7.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | brcm,usb-pinmap.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/brcm,usb-pinmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom USB pin map Controller
10 - Al Cooper <alcooperx@gmail.com>
15 - const: brcm,usb-pinmap
22 description: Interrupt for signals mirrored to out-gpios.
24 in-gpios:
29 brcm,in-functions:
[all …]
|
| /freebsd/contrib/ntp/html/drivers/ |
| H A D | driver22.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
7 <!-- Changed by: Harlan &, 31-Mar-2014 -->
14 <!-- #BeginDate format:En2m -->31-Mar-2014 07:46<!-- #EndDate -->
23 …te configuration and was poorly documented. This driver requires the Pulse per Second API (PPSAPI)…
25 …-per-second (PPS) signal produced by a cesium clock, radio clock or related devices. It can be use…
27 …y versions of Tru64 (Alpha) and SunOS. See the <a href="../pps.html">Pulse-per-second (PPS) Signal…
31 pin (DB-9 pin 1, DB-25 pin 8) of the same connector. In some systems
33 be connected directly to the ACK pin (DB25 pin 10) of the connector.
58 and Earth only one or two times per Sol (Mars day). These orbiters have a
[all …]
|
| /freebsd/share/misc/ |
| H A D | scsi_modes | 35 # 'i' is a byte-sized integral types, followed by a field width of
38 # 'b' is a bit-sized integral type
39 # 't' is a bitfield type- followed by a bit field width
42 # 'z' values are null-padded strings
81 {Extended Self-Test Completion Time} i2
95 0x02 "Disconnect-Reconnect" {
111 0x16 "Extended Device-Type Specific";
154 0x18 "Protocol-Specific Logical Unit";
156 0x19 "Protocol-Specific Port";
172 {Background Pre-Scan Time Limit} i2
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/iio/dac/ |
| H A D | ti,dac7612.txt | 1 * Texas Instruments Dual, 12-Bit Serial Input Digital-to-Analog Converter
3 The DAC7612 is a dual, 12-bit digital-to-analog converter (DAC) with guaranteed
4 12-bit monotonicity performance over the industrial temperature range.
7 The internal DACs are loaded when the LOADDACS pin is pulled down.
12 - compatible: Should be one of:
16 - reg: Definition as per Documentation/devicetree/bindings/spi/spi-bus.txt
19 - ti,loaddacs-gpios: GPIO descriptor for the LOADDACS pin.
20 - spi-*: Definition as per Documentation/devicetree/bindings/spi/spi-bus.txt
27 ti,loaddacs-gpios = <&msmgpio 25 GPIO_ACTIVE_LOW>;
|
| /freebsd/sys/contrib/device-tree/Bindings/display/tilcdc/ |
| H A D | panel.txt | 1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
|
| /freebsd/sys/sys/ |
| H A D | gpio.h | 3 /*-
4 * SPDX-License-Identifier: (BSD-2-Clause AND ISC)
58 /* GPIO pin states */
62 /* Max name length of a pin */
65 /* GPIO pin configuration flags */
68 #define GPIO_PIN_OPENDRAIN 0x00000004 /* open-drain output */
69 #define GPIO_PIN_PUSHPULL 0x00000008 /* push-pull output */
71 #define GPIO_PIN_PULLUP 0x00000020 /* internal pull-up enabled */
72 #define GPIO_PIN_PULLDOWN 0x00000040 /* internal pull-down enabled */
76 #define GPIO_PIN_PRESET_LOW 0x00000400 /* preset pin to high or */
[all …]
|
| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_gpio.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2012-2015 Luiz Otavio O Souza <loos@FreeBSD.org>
96 { -1, 0, 0 }
101 uint32_t pin; member
135 #define BCM_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
136 #define BCM_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
137 #define BCM_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
139 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
141 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
[all …]
|
| /freebsd/sys/contrib/device-tree/src/mips/mobileye/ |
| H A D | eyeq5-pins.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Default pin configuration for Mobileye EyeQ5 boards. We mostly create one
5 * pin configuration node per function.
9 timer0_pins: timer0-pins {
13 timer1_pins: timer1-pins {
17 timer2_pins: timer2-pins {
21 pps0_pins: pps0-pin {
25 pps1_pins: pps1-pin {
29 timer5_ext_pins: timer5-ext-pins {
33 timer5_ext_input_pins: timer5-ext-input-pins {
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | xlnx,fpga-selectmap.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Charles Perry <charles.perry@savoirfairelinux.com>
15 the x8 mode is supported where data is loaded at one byte per rising edge of
16 the clock, with the MSB of each byte presented to the D0 pin.
22 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
27 - xlnx,fpga-xc7s-selectmap
28 - xlnx,fpga-xc7a-selectmap
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/extcon/ |
| H A D | wlf,arizona.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
20 wlf,hpdet-channel:
30 wlf,use-jd2:
32 Use the additional JD input along with JD1 for dual pin jack detection.
35 wlf,use-jd2-nopull:
40 wlf,jd-invert:
45 wlf,micd-software-compare:
[all …]
|