/linux/include/linux/phy/ |
H A D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set 34 * lane 0, used for the transmissions on main link. 44 * to be used by particular lanes. One value per lane. 45 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc. 54 * Pre-emphasis levels, as specified by DisplayPort specification, to be 55 * used by particular lanes. One value per lane. 64 * Flag indicating, whether or not to enable spread-spectrum clocking. 81 * Flag indicating, whether or not reconfigure lane count to 91 * and pre-emphasis to requested values. Only lanes specified
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H A D | phy-lvds.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 10 * struct phy_configure_opts_lvds - LVDS configuration set 11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential 16 * data lanes, starting from lane 0,
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/linux/Documentation/devicetree/bindings/media/ |
H A D | video-interfaces.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sakari Ailus <sakari.ailus@linux.intel.com> 11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 29 #address-cells = <1>; 30 #size-cells = <0>; 45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is 49 specify #address-cells, #size-cells properties independently for the 'port' [all …]
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/linux/drivers/phy/ |
H A D | phy-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * AppliedMicro X-Gene Multi-purpose PHY driver 10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes. 19 * ----------------- 20 * | Internal | |------| 21 * | Ref PLL CMU |----| | ------------- --------- 22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes| 23 * | | | | --------- 24 * External Clock ------| | ------------- 25 * |------| [all …]
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/linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
H A D | uncore-io.json | 13 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 29 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 145 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", 152 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", 164 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 176 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 188 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 200 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 212 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 224 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… [all …]
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/linux/drivers/gpu/drm/i915/display/ |
H A D | vlv_dpio_phy_regs.h | 1 /* SPDX-License-Identifier: MIT */ 12 #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4) 13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */ 15 #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */ 19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument 24 * Per pipe/PLL DPIO regs 29 #define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */ 30 #define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */ 70 * Per DDI channel DPIO regs 156 #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument [all …]
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/linux/tools/perf/pmu-events/arch/x86/icelakex/ |
H A D | uncore-io.json | 114 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", 121 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", 133 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 145 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 157 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 169 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 181 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 193 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 205 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… 217 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane… [all …]
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/linux/Documentation/devicetree/bindings/media/i2c/ |
H A D | st,st-mipid02.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge 10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com> 11 - Sylvain Petinot <sylvain.petinot@foss.st.com> 14 MIPID02 has two CSI-2 input ports, only one of those ports can be 15 active at a time. Active port input stream will be de-serialized 17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 [all …]
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H A D | imx219.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor 10 - Dave Stevenson <dave.stevenson@raspberrypi.com> 12 description: |- 13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor 15 I2C interface. The I2C address is fixed to 0x10 as per sensor data sheet. 16 Image data is sent through MIPI CSI-2, which is configured as either 2 or 30 VDIG-supply: [all …]
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H A D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge 3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts 4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C. 8 - compatible: value should be "toshiba,tc358743" 9 - clocks, clock-names: should contain a phandle link to the reference clock 14 - reset-gpios: gpio phandle GPIO connected to the reset pin 15 - interrupts: GPIO connected to the interrupt pin 16 - data-lanes: should be <1 2 3 4> for four-lane operation, 17 or <1 2> for two-lane operation 18 - clock-lanes: should be <0> [all …]
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H A D | thine,thp7312.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Paul Elder <paul.elder@@ideasonboard.com> 17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2 23 - $ref: /schemas/media/video-interface-devices.yaml# 36 thine,boot-mode: 43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from 46 reset-gpios: 52 vddcore-supply: [all …]
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/linux/Documentation/admin-guide/perf/ |
H A D | dwc_pcie_pmu.rst | 9 Port in a Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error 17 - one 64-bit counter for Time Based Analysis (RX/TX data throughput and 18 time spent in each low-power LTSSM state) and 19 - one 32-bit counter for Event Counting (error and non-error events for 20 a specified lane) 25 ------------------- 28 throughput and time spent in each low-power LTSSM state by the controller. 31 - Group#0: Percentage of time the controller stays in LTSSM states. 32 - Group#1: Amount of data processed (Units of 16 bytes). 34 Lane Event counters [all …]
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/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-pcie-msm8996.c | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <linux/clk-provider.h> 22 #include "phy-qcom-qmp-common.h" 24 #include "phy-qcom-qmp.h" 36 /* set of registers with offsets different per-PHY */ 139 /* struct qmp_phy_cfg - per-PHY initialization config */ 144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 169 * struct qmp_phy - per-lane phy descriptor 174 * @tx: iomapped memory space for lane's tx 175 * @rx: iomapped memory space for lane's rx [all …]
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/linux/drivers/gpu/drm/tegra/ |
H A D | dp.h | 1 /* SPDX-License-Identifier: MIT */ 3 * Copyright (C) 2013-2019 NVIDIA Corporation. 18 * struct drm_dp_link_caps - DP link capabilities 61 * struct drm_dp_link_ops - DP link operations 80 * struct drm_dp_link_train_set - link training settings 81 * @voltage_swing: per-lane voltage swing 82 * @pre_emphasis: per-lane pre-emphasis 83 * @post_cursor: per-lane post-cursor 92 * struct drm_dp_link_train - link training state information 110 * struct drm_dp_link - DP link capabilities and configuration
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 signals) which connect directly to pins/pads on the SoC package. Each lane 18 and thus contains any logic common to all its lanes. Each lane can be 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
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H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 signals) which connect directly to pins/pads on the SoC package. Each lane 18 and thus contains any logic common to all its lanes. Each lane can be 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
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H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 signals) which connect directly to pins/pads on the SoC package. Each lane 18 and thus contains any logic common to all its lanes. Each lane can be 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
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H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 signals) which connect directly to pins/pads on the SoC package. Each lane 18 and thus contains any logic common to all its lanes. Each lane can be 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
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H A D | phy-cadence-torrent.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 16 - Swapnil Jakhade <sjakhade@cadence.com> 17 - Yuti Amonkar <yamonkar@cadence.com> 22 - cdns,torrent-phy 23 - ti,j7200-serdes-10g 24 - ti,j721e-serdes-10g 26 '#address-cells': [all …]
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/linux/net/atm/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 9 ATM is a high-speed networking technology for Local Area Networks 18 Note that you need a set of user-space programs to actually make use 29 (LANE)" below. 42 tristate "LAN Emulation (LANE) support" 47 LANE client can also act as an proxy client bridging packets between 48 ELAN and Ethernet segments. You need LANE if you want to try MPOA. 51 tristate "Multi-Protocol Over ATM (MPOA) support" 54 Multi-Protocol Over ATM allows ATM edge devices such as routers, 69 bool "Per-VC IP filter kludge" [all …]
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/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | ps8640.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Nicolas Boichat <drinkcat@chromium.org> 13 The PS8640 is a low power MIPI-to-eDP video format converter supporting 16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The 18 3.24Gbit/sec per lane. 28 powerdown-gpios: 32 reset-gpios: 36 vdd12-supply: [all …]
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/linux/Documentation/driver-api/nvdimm/ |
H A D | btt.rst | 2 BTT - Block Translation Table 14 using stored energy in capacitors to complete in-flight block writes, or perhaps 15 in firmware. We don't have this luxury with persistent memory - if a write is in 23 the heart of it, is an indirection table that re-maps all the blocks on the 37 next arena). The following depicts the "On-disk" metadata layout:: 40 Backing Store +-------> Arena 41 +---------------+ | +------------------+ 43 | Arena 0 +---+ | 4K | 44 | 512G | +------------------+ 46 +---------------+ | | [all …]
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/linux/drivers/media/pci/intel/ipu6/ |
H A D | ipu6-platform-isys-csi2-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (C) 2023--2024 Intel Corporation */ 19 * IRQ0 - CSI_FE event 20 * IRQ1 - CSI_SYNC 21 * IRQ2 - S2M_SIDS0TO7 22 * IRQ3 - S2M_SIDS8TO15 141 * ipu6se support 2 front ends, 2 port per front end, 4 ports 0..3 142 * sip0 - 0, 1 143 * sip1 - 2, 3 169 #define CSI2_SIP_TOP_CSI_RX_DLY_CNT_TERMEN_DLANE(lane) (0xc + (lane) * 8) argument [all …]
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | atombios_dp.c | 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 34 #include "atom-bits.h" 63 struct drm_device *dev = chan->dev; in amdgpu_atombios_dp_process_aux_ch() 73 mutex_lock(&chan->mutex); in amdgpu_atombios_dp_process_aux_ch() 75 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1); in amdgpu_atombios_dp_process_aux_ch() 82 args.v2.ucChannelID = chan->rec.i2c_id; in amdgpu_atombios_dp_process_aux_ch() 84 args.v2.ucHPD_ID = chan->rec.hpd; in amdgpu_atombios_dp_process_aux_ch() 86 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_dp_process_aux_ch() 92 r = -ETIMEDOUT; in amdgpu_atombios_dp_process_aux_ch() 99 r = -EIO; in amdgpu_atombios_dp_process_aux_ch() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/link/ |
H A D | link_validation.c | 41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz() 43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_tmds_output_pixel_clock_100hz() 45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in get_tmds_output_pixel_clock_100hz() 48 if (timing->display_color_depth == COLOR_DEPTH_101010) in get_tmds_output_pixel_clock_100hz() 50 else if (timing->display_color_depth == COLOR_DEPTH_121212) in get_tmds_output_pixel_clock_100hz() 60 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps; in dp_active_dongle_validate_timing() 62 switch (dpcd_caps->dongle_type) { in dp_active_dongle_validate_timing() 66 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) in dp_active_dongle_validate_timing() 74 if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER && in dp_active_dongle_validate_timing() 75 dongle_caps->extendedCapValid == true) { in dp_active_dongle_validate_timing() [all …]
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