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/linux/include/linux/phy/
H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
34 * lane 0, used for the transmissions on main link.
44 * to be used by particular lanes. One value per lane.
45 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
54 * Pre-emphasis levels, as specified by DisplayPort specification, to be
55 * used by particular lanes. One value per lane.
64 * Flag indicating, whether or not to enable spread-spectrum clocking.
81 * Flag indicating, whether or not reconfigure lane count to
91 * and pre-emphasis to requested values. Only lanes specified
H A Dphy-lvds.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
16 * data lanes, starting from lane 0,
/linux/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
14 /* General registers per SerDes block */
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
26 /* Per PLL registers */
45 /* Per SerDes lane registers */
46 /* Lane a General Control Register */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
55 /* Lane a Tx Reset Control Register */
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
[all …]
/linux/Documentation/admin-guide/perf/
H A Ddwc_pcie_pmu.rst9 Port in a Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error
17 - one 64-bit counter for Time Based Analysis (RX/TX data throughput and
18 time spent in each low-power LTSSM state) and
19 - one 32-bit counter per event for Event Counting (error and non-error
20 events for a specified lane)
25 -------------------
28 throughput and time spent in each low-power LTSSM state by the controller.
31 - Group#0: Percentage of time the controller stays in LTSSM states.
32 - Group#1: Amount of data processed (Units of 16 bytes).
34 Lane Event counters
[all …]
/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-io.json13 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
29 …, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
145 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
152 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
164 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
176 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
188 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
200 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
212 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
224 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h1 /* SPDX-License-Identifier: MIT */
12 #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
15 #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
24 * Per pipe/PLL DPIO regs
29 #define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */
30 #define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */
70 * Per DDI channel DPIO regs
156 #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
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/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-io.json114 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
121 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
133 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
145 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
157 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
169 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
181 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
193 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
205 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
217 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
36 /* set of registers with offsets different per-PHY */
139 /* struct qmp_phy_cfg - per-PHY initialization config */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
169 * struct qmp_phy - per-lane phy descriptor
174 * @tx: iomapped memory space for lane's tx
175 * @rx: iomapped memory space for lane's rx
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g
24 - ti,j721e-serdes-10g
26 '#address-cells':
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/linux/net/atm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 ATM is a high-speed networking technology for Local Area Networks
18 Note that you need a set of user-space programs to actually make use
29 (LANE)" below.
42 tristate "LAN Emulation (LANE) support"
47 LANE client can also act as an proxy client bridging packets between
48 ELAN and Ethernet segments. You need LANE if you want to try MPOA.
51 tristate "Multi-Protocol Over ATM (MPOA) support"
54 Multi-Protocol Over ATM allows ATM edge devices such as routers,
69 bool "Per-VC IP filter kludge"
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dsony,imx219.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
15 I2C interface. The I2C address is fixed to 0x10 as per sensor data sheet.
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
20 - $ref: /schemas/media/video-interface-devices.yaml#
[all …]
H A Dthine,thp7312.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Elder <paul.elder@@ideasonboard.com>
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
23 - $ref: /schemas/media/video-interface-devices.yaml#
36 thine,boot-mode:
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
46 reset-gpios:
52 vddcore-supply:
[all …]
/linux/Documentation/driver-api/nvdimm/
H A Dbtt.rst2 BTT - Block Translation Table
14 using stored energy in capacitors to complete in-flight block writes, or perhaps
15 in firmware. We don't have this luxury with persistent memory - if a write is in
23 the heart of it, is an indirection table that re-maps all the blocks on the
37 next arena). The following depicts the "On-disk" metadata layout::
40 Backing Store +-------> Arena
41 +---------------+ | +------------------+
43 | Arena 0 +---+ | 4K |
44 | 512G | +------------------+
46 +---------------+ | |
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
16 plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
18 3.24Gbit/sec per lane.
28 powerdown-gpios:
32 reset-gpios:
36 vdd12-supply:
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-platform-isys-csi2-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2023--2024 Intel Corporation */
19 * IRQ0 - CSI_FE event
20 * IRQ1 - CSI_SYNC
21 * IRQ2 - S2M_SIDS0TO7
22 * IRQ3 - S2M_SIDS8TO15
141 * ipu6se support 2 front ends, 2 port per front end, 4 ports 0..3
142 * sip0 - 0, 1
143 * sip1 - 2, 3
169 #define CSI2_SIP_TOP_CSI_RX_DLY_CNT_TERMEN_DLANE(lane) (0xc + (lane) * 8) argument
[all …]
/linux/drivers/soundwire/
H A Dgeneric_bandwidth_allocation.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
21 unsigned int lane; member
42 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
44 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
46 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_slave_ports()
47 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
48 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
49 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
52 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in sdw_compute_slave_ports()
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
73 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
75 if (!dp->force_hpd) in analogix_dp_detect_hpd()
76 return -ETIMEDOUT; in analogix_dp_detect_hpd()
83 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
88 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
89 return -EINVAL; in analogix_dp_detect_hpd()
92 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
102 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
104 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
[all …]
/linux/drivers/net/ethernet/sfc/falcon/
H A Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
69 /* Lane power-down */
79 /* Bit position of value for lane 0 (or 2) */
81 /* Bit position of value for lane 1 (or 3) */
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
41 calxeda,led-order:
43 $ref: /schemas/types.yaml#/definitions/uint32-array
[all …]
/linux/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
H A Dcsi_rx_public.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 * Get the state of the csi rx frontend regiester-set.
20 * @param[out] state Point to the register-state.
27 * Dump the state of the csi rx frontend regiester-set.
30 * @param[in] state Point to the register-state.
37 * Get the state of the register set per dlane process.
39 * @param[in] id The global unique ID of the input-buffer controller.
40 * @param[in] lane The lane ID.
45 const u32 lane,
49 * Get the state of the csi rx backend regiester-set.
[all …]

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