Lines Matching +full:per +full:- +full:lane
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
34 #include "atom-bits.h"
63 struct drm_device *dev = chan->dev;
73 mutex_lock(&chan->mutex);
75 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
82 args.v2.ucChannelID = chan->rec.i2c_id;
84 args.v2.ucHPD_ID = chan->rec.hpd;
86 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
92 r = -ETIMEDOUT;
99 r = -EIO;
106 r = -EIO;
119 mutex_unlock(&chan->mutex);
137 if (WARN_ON(msg->size > 16))
138 return -E2BIG;
140 tx_buf[0] = msg->address & 0xff;
141 tx_buf[1] = msg->address >> 8;
142 tx_buf[2] = (msg->request << 4) |
143 ((msg->address >> 16) & 0xf);
144 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
146 switch (msg->request & ~DP_AUX_I2C_MOT) {
152 tx_size = HEADER_SIZE + msg->size;
153 if (msg->size == 0)
157 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
162 ret = msg->size;
170 if (msg->size == 0)
175 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
178 ret = -EINVAL;
183 msg->reply = ack >> 4;
190 amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
191 amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
192 amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev;
194 drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux);
195 amdgpu_connector->ddc_bus->has_aux = true;
209 int lane;
211 for (lane = 0; lane < lane_count; lane++) {
212 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
213 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
215 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
216 lane,
236 for (lane = 0; lane < 4; lane++)
237 train_set[lane] = v | p;
240 /* convert bits per color to bits per pixel */
287 return -EINVAL;
304 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
310 struct drm_device *dev = amdgpu_connector->base.dev;
314 amdgpu_connector->ddc_bus->rec.i2c_id, 0);
319 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
322 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
325 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
329 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
336 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) {
340 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux,
342 dig_connector->downstream_ports,
345 memset(dig_connector->downstream_ports, 0,
352 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
356 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV,
359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
361 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
362 dig_connector->dpcd);
369 dig_connector->dpcd[0] = 0;
370 return -EINVAL;
381 if (!amdgpu_connector->con_priv)
386 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
396 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
398 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
415 if (!amdgpu_connector->con_priv)
417 dig_connector = amdgpu_connector->con_priv;
419 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
420 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
421 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
422 mode->clock,
423 &dig_connector->dp_lane_count,
424 &dig_connector->dp_clock);
426 dig_connector->dp_clock = 0;
427 dig_connector->dp_lane_count = 0;
440 if (!amdgpu_connector->con_priv)
442 dig_connector = amdgpu_connector->con_priv;
444 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd,
445 mode->clock, &dp_lanes, &dp_clock);
459 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
461 if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
464 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
475 if (!amdgpu_connector->con_priv)
478 dig_connector = amdgpu_connector->con_priv;
481 if (dig_connector->dpcd[0] >= 0x11) {
482 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
506 amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
508 0, dp_info->train_set[0]); /* sets all lanes at once */
511 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
512 dp_info->train_set, dp_info->dp_lane_count);
532 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
535 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
541 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
542 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
546 amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
549 if (dp_info->dpcd[3] & 0x1)
550 drm_dp_dpcd_writeb(dp_info->aux,
553 drm_dp_dpcd_writeb(dp_info->aux,
556 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
557 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
559 /* set the lane count on the sink */
560 tmp = dp_info->dp_lane_count;
561 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
563 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
566 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
567 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
570 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
574 drm_dp_dpcd_writeb(dp_info->aux,
587 drm_dp_dpcd_writeb(dp_info->aux,
592 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
606 memset(dp_info->train_set, 0, 4);
613 dp_info->tries = 0;
616 drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);
618 if (drm_dp_dpcd_read_link_status(dp_info->aux,
619 dp_info->link_status) <= 0) {
624 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
629 for (i = 0; i < dp_info->dp_lane_count; i++) {
630 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
633 if (i == dp_info->dp_lane_count) {
638 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
639 ++dp_info->tries;
640 if (dp_info->tries == 5) {
645 dp_info->tries = 0;
647 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
650 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
651 dp_info->train_set);
657 return -1;
659 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
660 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
661 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
672 if (dp_info->tp3_supported)
678 dp_info->tries = 0;
681 drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);
683 if (drm_dp_dpcd_read_link_status(dp_info->aux,
684 dp_info->link_status) <= 0) {
689 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
695 if (dp_info->tries > 5) {
701 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
702 dp_info->train_set);
705 dp_info->tries++;
710 return -1;
712 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
713 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
714 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
723 struct drm_device *dev = encoder->dev;
731 if (!amdgpu_encoder->enc_priv)
735 if (!amdgpu_connector->con_priv)
737 dig_connector = amdgpu_connector->con_priv;
739 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
740 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
743 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
753 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
757 dp_info.dp_lane_count = dig_connector->dp_lane_count;
758 dp_info.dp_clock = dig_connector->dp_clock;
759 dp_info.aux = &amdgpu_connector->ddc_bus->aux;